Displaying 7 results from an estimated 7 matches for "c3e58da".
2016 Oct 17
2
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...(push, 0x00000000);
> + PUSH_TIC (push, bo, 0, ppix->drawable.width, ppix->drawable.height, 0,
> + format);
>
> PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
> if (ppict->repeat) {
> diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
> index 129c505..c3e58da 100644
> --- a/src/nvc0_xv.c
> +++ b/src/nvc0_xv.c
> @@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
> { dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
> };
> struct nouveau_pushbuf *push = pNv->pushbuf;
> - uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode...
2016 Oct 16
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...(push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
+ PUSH_TIC (push, bo, 0, ppix->drawable.width, ppix->drawable.height, 0,
+ format);
PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
if (ppict->repeat) {
diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
index 129c505..c3e58da 100644
--- a/src/nvc0_xv.c
+++ b/src/nvc0_xv.c
@@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
{ dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
};
struct nouveau_pushbuf *push = pNv->pushbuf;
- uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode << 18);
float X1, X2, Y1, Y...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...(push, 0x03000000);
- PUSH_DATA (push, 0x00000000);
+ PUSH_TIC (push, bo, 0, ppix->drawable.width, ppix->drawable.height, 0,
+ format);
PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
if (ppict->repeat) {
diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
index 129c505..c3e58da 100644
--- a/src/nvc0_xv.c
+++ b/src/nvc0_xv.c
@@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
{ dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
};
struct nouveau_pushbuf *push = pNv->pushbuf;
- uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode << 18);
float X1, X2, Y1, Y...
2016 Oct 17
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...t;drawable.width,
>> ppix->drawable.height, 0,
>> + format);
>>
>> PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
>> if (ppict->repeat) {
>> diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
>> index 129c505..c3e58da 100644
>> --- a/src/nvc0_xv.c
>> +++ b/src/nvc0_xv.c
>> @@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
>> { dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
>> };
>> struct nouveau_pushbuf *push = pNv->pushbuf;
>> - u...
2016 Oct 27
2
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...(push, 0x00000000);
> + PUSH_TIC (push, bo, 0, ppix->drawable.width, ppix->drawable.height, 0,
> + format);
>
> PUSH_DATAu(push, pNv->scratch, TSC_OFFSET + (unit * 32), 8);
> if (ppict->repeat) {
> diff --git a/src/nvc0_xv.c b/src/nvc0_xv.c
> index 129c505..c3e58da 100644
> --- a/src/nvc0_xv.c
> +++ b/src/nvc0_xv.c
> @@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
> { dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
> };
> struct nouveau_pushbuf *push = pNv->pushbuf;
> - uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode...
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
These are copied directly from the mesa repository.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++
src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++----------------
2 files changed, 892 insertions(+), 340 deletions(-)
create mode 100644 src/hwdefs/gm107_texture.xml.h
diff --git
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
I believe I've addressed all the feedback from the first time around, and
also made fixes necessary for GM20x based on testing results. I believe
now it should actually work for all GM10x and GM20x. Further, GP10x should
be very easy to add, but without someone to actually test I didn't want to
claim support for it.
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update