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c36c4010
2018 Apr 26
1
[Constant Folder, InstCombine, ARM, AArch64] Question about constant folding of vector load
Hello,
There is a particular code sequence I would like to optimize at the IR level.
I'd like to turn an Arm/AArch64 table lookup intrinsic that takes a constant vector mask into a shufflevector instruction:
vtbl1(V,mask) ~> shufflevector(V,undef,mask)
The reason is that if the mask is {7,6,5,4,3,2,1,0}, then the backend will generate rev64 instructions instead.
If the mask comes