Displaying 3 results from an estimated 3 matches for "c2_cmpeqi".
2016 Mar 30
1
infer correct types from the pattern
On 3/30/2016 4:42 PM, Rail Shafigulin via llvm-dev wrote:
> i'm getting a
>
> Could not infer all types in pattern!
>
> error in my backend. it is happening on the following instruction:
>
> VGETITEM: (set GPR:{i32:f32}:$rD, (extractelt:{i32:f32}
> VR:{v4i32:v4f32}:$rA, GPR:i32:$rB)).
>
> how do i make it use appropriate types? in other words if it is f32 then
2019 Jun 30
6
[hexagon][PowerPC] code regression (sub-optimal code) on LLVM 9 when generating hardware loops, and the "llvm.uadd" intrinsic.
...ntregs = PHI %6:intregs, %bb.2, %4:intregs, %bb.4
%12:intregs, %4:intregs = L2_loadri_pi %2:intregs, 4 :: (load 4 from %ir.a.addr.03, !tbaa !2)
%5:intregs = S2_storeri_pi %1:intregs, 4, %12:intregs :: (store 4 into %ir.res.addr.04, !tbaa !2)
%3:intregs = A2_addi %0:intregs, 1
%13:predregs = C2_cmpeqi %3:intregs, 0
J2_jumpf %13:predregs, %bb.4, implicit-def dead $pc
J2_jump %bb.5, implicit-def dead $pc
The differences above allow LLVM 7 to turn %13, %3, %11 into a hardware Loop as shown in the assembly code earlier in this message. However, LLVM 9 can’t identify a Hardware loop pattern due...
2019 Jul 01
0
[hexagon][PowerPC] code regression (sub-optimal code) on LLVM 9 when generating hardware loops, and the "llvm.uadd" intrinsic.
...ntregs = PHI %6:intregs, %bb.2, %4:intregs, %bb.4
%12:intregs, %4:intregs = L2_loadri_pi %2:intregs, 4 :: (load 4 from %ir.a.addr.03, !tbaa !2)
%5:intregs = S2_storeri_pi %1:intregs, 4, %12:intregs :: (store 4 into %ir.res.addr.04, !tbaa !2)
%3:intregs = A2_addi %0:intregs, 1
%13:predregs = C2_cmpeqi %3:intregs, 0
J2_jumpf %13:predregs, %bb.4, implicit-def dead $pc
J2_jump %bb.5, implicit-def dead $pc
The differences above allow LLVM 7 to turn %13, %3, %11 into a hardware Loop as shown in the assembly code earlier in this message. However, LLVM 9 can’t identify a Hardware loop pattern due...