Displaying 4 results from an estimated 4 matches for "c028b8c5".
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c028b8c0
2007 Apr 18
0
[PATCH 1/12] gdt-tss-redundant
...as already cleared
the busy bit.
Commented disassembly, line 1:
c028b8bd: 8b 0c 86 mov (%esi,%eax,4),%ecx
c028b8c0: 01 cb add %ecx,%ebx
c028b8c2: 8d 0c 39 lea (%ecx,%edi,1),%ecx
=> %ecx = per_cpu(cpu_gdt_table, cpu)
c028b8c5: 8d 91 80 00 00 00 lea 0x80(%ecx),%edx
=> %edx = &per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_TSS]
c028b8cb: 66 c7 42 00 73 20 movw $0x2073,0x0(%edx)
c028b8d1: 66 89 5a 02 mov %bx,0x2(%edx)
c028b8d5: c1 cb 10 ror $0x10,%...
2007 Apr 18
0
[PATCH 1/12] gdt-tss-redundant
...as already cleared
the busy bit.
Commented disassembly, line 1:
c028b8bd: 8b 0c 86 mov (%esi,%eax,4),%ecx
c028b8c0: 01 cb add %ecx,%ebx
c028b8c2: 8d 0c 39 lea (%ecx,%edi,1),%ecx
=> %ecx = per_cpu(cpu_gdt_table, cpu)
c028b8c5: 8d 91 80 00 00 00 lea 0x80(%ecx),%edx
=> %edx = &per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_TSS]
c028b8cb: 66 c7 42 00 73 20 movw $0x2073,0x0(%edx)
c028b8d1: 66 89 5a 02 mov %bx,0x2(%edx)
c028b8d5: c1 cb 10 ror $0x10,%...
2007 Apr 18
3
[PATCH] abstract out bits of ldt.c
Chris Wright wrote:
>* Zachary Amsden (zach@vmware.com) wrote:
>
>
>>Does Xen assume page aligned descriptor tables? I assume from this
>>
>>
>
>Yes.
>
>
>
>>patch and snippets I have gathered from others, that is a yes, and other
>>things here imply that DT pages are not shadowed. If so, Xen itself
>>must have live segments
2007 Apr 18
3
[PATCH] abstract out bits of ldt.c
Chris Wright wrote:
>* Zachary Amsden (zach@vmware.com) wrote:
>
>
>>Does Xen assume page aligned descriptor tables? I assume from this
>>
>>
>
>Yes.
>
>
>
>>patch and snippets I have gathered from others, that is a yes, and other
>>things here imply that DT pages are not shadowed. If so, Xen itself
>>must have live segments