Displaying 1 result from an estimated 1 matches for "byte&word".
2013 Nov 21
1
[LLVMdev] Modelling M68k registers?
...t named but denoted by the size
of the operation. Compare these two:
16bit mem to reg: "mov ax, [ebx] -> move.w (a0), d1"
32bit mem to reg: "mov eax, [ebx] -> move.l (a0), d1"
This makes me think that maybe subregs is not what I should use, but
instead treat it as the byte&word load and store in ARM? Or maybe I
should treat data and address registers differently since writing to
the 'subregs' of a data reg to not change the upper bits, whereas with
address registers all 32bits are signed extended, as in:
move.l #$12345678, d0
move.w #$fedc, d0 ; d...