search for: burr

...nly if (isProfitableToConv3Addr(regA, regB)) { That gave me test.inc.s where lea replaced with inc+mov and this code is ~27% faster on my Westmere system. IACA throughput analysis gives 11 cycles for new block. But the best performance I've got from switching scheduling algorithm from ILP to BURR (test.burr.s). It gives a few percent more vs. "ILP+INC" and I'm not sure why - it might be because test.burr.s has less instructions (no two moves that copy index) or it might be because additions scheduled differently. BURR puts loads and FP mul between additions, which are gathered...

On 17.09.2013, at 20:04, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Hi Andy, > > We have done some experimental evaluation of the different schedulers in LLVM 3.3 (source, BURR, ILP, fast, MI). The evaluation was done on x86-64 using SPEC CPU2006. We have measured both the amount of spill code as well as the execution time as detailed below. > > Here are our main findings: > > 1. The SD schedulers significantly impact the spill counts and the execution times...

I simulate a uniform data and then transformed into Burr(1,3,1) data, which is of pdf: f(x)=[3*(x^2)] / [(1+x^3)^2], x>0 How can I perform a goodness-of-fit test (k-s, anderson-darling,chisq,cramer-von mises,...) on it (should highly accept) to get test-statistics & p-values? Thanks! Sincerely, Shelton Jin -.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-....

...m-ld bar.bc] -> bar.opt.bc // [llc bar.opt.bc] -> bar.s ** Use of -g causes llvm-ld to run with -disable-opt $ mcc16 -S -g foo.c // [clang-cc foo.c] -> foo.bc // [llvm-ld -disable-opt foo.bc] -> foo.opt.bc // [llc foo.opt.bc] -> foo.s ** -I is passed to clang-cc, -pre-RA-sched=list-burr to llc. $ mcc16 -S -g -I ../include -pre-RA-sched=list-burr foo.c // [clang-cc -I ../include foo.c] -> foo.bc // [llvm-ld -disable-opt foo.bc] -> foo.opt.bc // [llc -pre-RA-sched=list-burr foo.opt.bc] -> foo.s ** -Wo passes options to llvm-ld $ mcc16 -Wo=opt1,opt2 -S -I ../include -pre-RA...

...gt; > > > That gave me test.inc.s where lea replaced with inc+mov and this code is > ~27% faster on my Westmere system. IACA throughput analysis gives 11 cycles > for new block. > > > > But the best performance I’ve got from switching scheduling algorithm from > ILP to BURR (test.burr.s). It gives a few percent more vs. “ILP+INC” and I’m > not sure why – it might be because test.burr.s has less instructions (no two > moves that copy index) or it might be because additions scheduled > differently. BURR puts loads and FP mul between additions, which are > ga...

...vm-ld to run with -disable-opt > $ mcc16 -S -g foo.c $ mcc16 -dry-run -S -g foo.c clang-cc foo.c -o /tmp/llvm_oQFmVn/foo.bc llvm-ld -disable-opt /tmp/llvm_oQFmVn/foo.bc -o /tmp/llvm_oQFmVn/foo.bc llc -f /tmp/llvm_oQFmVn/foo.bc -o foo.s > ** -I is passed to clang-cc, -pre-RA-sched=list-burr to llc. > $ mcc16 -S -g -I ../include -pre-RA-sched=list-burr foo.c $ mcc16 -dry-run -S -g -I ../include -pre-RA-sched=list-burr foo.c clang-cc -I ../include foo.c -o /tmp/llvm_5VxNFQ/foo.bc llvm-ld -disable-opt /tmp/llvm_5VxNFQ/foo.bc -o /tmp/llvm_5VxNFQ/foo.bc llc -pre-RA-sched list-burr -f...

...test.inc.s where lea replaced with inc+mov and this code is >> ~27% faster on my Westmere system. IACA throughput analysis gives 11 cycles >> for new block. >> >> >> >> But the best performance I’ve got from switching scheduling algorithm from >> ILP to BURR (test.burr.s). It gives a few percent more vs. “ILP+INC” and I’m >> not sure why – it might be because test.burr.s has less instructions (no two >> moves that copy index) or it might be because additions scheduled >> differently. BURR puts loads and FP mul between additions, which...

Hi Andy, We have done some experimental evaluation of the different schedulers in LLVM 3.3 (source, BURR, ILP, fast, MI). The evaluation was done on x86-64 using SPEC CPU2006. We have measured both the amount of spill code as well as the execution time as detailed below. Here are our main findings: 1. The SD schedulers significantly impact the spill counts and the execution times for many benchmarks...

...19, 2013 4:53 PM Subject: Re: [LLVMdev] Experimental Evaluation of the Schedulers in LLVM 3.3 On 17.09.2013, at 20:04, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Hi Andy, > > We have done some experimental evaluation of the different schedulers in LLVM 3.3 (source, BURR, ILP, fast, MI). The evaluation was done on x86-64 using SPEC CPU2006. We have measured both the amount of spill code as well as the execution time as detailed below. > > Here are our main findings: > > 1. The SD schedulers significantly impact the spill counts and the execution times...

Hi, Please see the two ".ll' files attached. Command line used llc -march=pic16 -pre-RA-sched=list-burr -regalloc=pbqp new.obc The above test case crashes only when I use the combination of list-burr scheduler and pbqp register allocator. If any of them (scheduler or register allocator) is replaced with some alternate then I don't see the crash. I could not figure out the reason. Please...

Hi Sanjiv, Sanjiv Gupta <sanjiv.gupta <at> microchip.com> writes: > > PIC16 now has clang and llc based system to generate native assembly. We > then use our native assembler (gpasm) and the native linker (mplink) to > generate the final executable. How can I integrate these things with > the driver llvmc to have gcc like user experience? Note that we also >

PIC16 now has clang and llc based system to generate native assembly. We then use our native assembler (gpasm) and the native linker (mplink) to generate the final executable. How can I integrate these things with the driver llvmc to have gcc like user experience? Note that we also want to run llvm-ld in order to perform the LTOs in case of multiple files. - Sanjiv

...ection Instruction ? What is the input ? 2. Where is described how the variations of List Scheduling work, in -pre-RA-sched phase ? -pre-RA-sched - Instruction schedulers available (before register allocation): =source - Similar to list-burr but schedules in source order when possible =list-tdrr - Top-down register reduction list scheduling =list-burr - Bottom-up register reduction list scheduling =list-td - Top-down list scheduler...

Dear LLVM'ers, I am browsing the instruction schedulers available in llc, and there are many: -pre-RA-sched = {default, none, simple, simple-noitin, list-burr, list-tdrr, list-td} I looked into the sources in lib/CodeGen/SelectionDAG, and I could find implementation of Sethi-Ullman numbering, list scheduling, etc. Now, I wish I could find some comparison between the schedulers. I guess you guys probably have some tests somewhere. Basically,...

...; > $ mcc16 -S -g foo.c > > $ mcc16 -dry-run -S -g foo.c > clang-cc foo.c -o /tmp/llvm_oQFmVn/foo.bc > llvm-ld -disable-opt /tmp/llvm_oQFmVn/foo.bc -o /tmp/llvm_oQFmVn/foo.bc > llc -f /tmp/llvm_oQFmVn/foo.bc -o foo.s > > > ** -I is passed to clang-cc, -pre-RA-sched=list-burr to llc. > > $ mcc16 -S -g -I ../include -pre-RA-sched=list-burr foo.c > > $ mcc16 -dry-run -S -g -I ../include -pre-RA-sched=list-burr foo.c > clang-cc -I ../include foo.c -o /tmp/llvm_5VxNFQ/foo.bc > llvm-ld -disable-opt /tmp/llvm_5VxNFQ/foo.bc -o /tmp/llvm_5VxNFQ/foo.bc > llc...

...comparing against and some information about the machine model that they are scheduling for.  So, it would be great if you could confirm or correct the following information and answer my questions below: The default scheduler for the x86-32 target is the bottom-up register-pressure reduction (BURR) scheduler, while for the x86-64 target it is the ILP Scheduler. According to the brief documentation in the source file ScheduleDAGRRList, the BURR is a register pressure reduction scheduler, while the ILP is a register-pressure aware scheduler that tries to balance ILP and register pressure....

...PBQP solver. I'm currently investigating. Cheers, Lang. On Thu, Nov 12, 2009 at 12:46 AM, <Sachin.Punyani at microchip.com> wrote: > Hi, > > > > Please see the two “.ll’ files attached. > > > > Command line used > > llc –march=pic16  –pre-RA-sched=list-burr –regalloc=pbqp new.obc > > > > The above test case crashes only when I use the combination of list-burr > scheduler and pbqp register allocator. If any of them (scheduler or register > allocator) is replaced with some alternate then I don’t see the crash. > > > > I cou...

...t; Lang. > > On Thu, Nov 12, 2009 at 12:46 AM,  <Sachin.Punyani at microchip.com> wrote: >> Hi, >> >> >> >> Please see the two “.ll’ files attached. >> >> >> >> Command line used >> >> llc –march=pic16  –pre-RA-sched=list-burr –regalloc=pbqp new.obc >> >> >> >> The above test case crashes only when I use the combination of list-burr >> scheduler and pbqp register allocator. If any of them (scheduler or register >> allocator) is replaced with some alternate then I don’t see the crash. &...

...ed with inc+mov and this code is >>> ~27% faster on my Westmere system. IACA throughput analysis gives 11 cycles >>> for new block. >>> >>> >>> >>> But the best performance I’ve got from switching scheduling algorithm from >>> ILP to BURR (test.burr.s). It gives a few percent more vs. “ILP+INC” and I’m >>> not sure why – it might be because test.burr.s has less instructions (no two >>> moves that copy index) or it might be because additions scheduled >>> differently. BURR puts loads and FP mul between addi...

On Jul 2, 2013, at 2:35 PM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Thank you for the answers! We are currently trying to test the MI scheduler. We are using LLVM 3.3 with Dragon Egg 3.3 on an x86-64 machine. So far, we have run one SPEC CPU2006 test with the MI scheduler enabled using the option -fplugin-arg-dragonegg-llvm-option='-enable-misched:true' with -O3.