Displaying 2 results from an estimated 2 matches for "builder_vector".
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2014 Jul 11
2
[LLVMdev] Lowering to return multiple values: codeGen, instruction write one value to the input register.
...return DAG.getMergeValues(Results, 2, DL);
“ which is used to lower an instruction that returns two values.
I am trying to something like this:
”
…….
SDValue z = DAG.getNode(my_ISD::test_op, DL, VT, Op.getOperand(0);
SDValue w = DAG.getConstant(1, MVT::i32);
SDValue DataZ = DAG.getNode(ISD::BUILDER_VECTOR, DL, MVT::v4i32, z, z, z, z);
SDValue DataW = DAG.getNode(ISD::BUILDER_VECTOR, DL, MVT::v4i32, w, w, w, w);
SDValue result[] = {DataZ, DataW};
return DAg.getMergeValues(results, 2, DL);
“
but my view-dag only shows one return value, wondering what is wrong?
should the results dags must be someho...
2014 Jul 07
2
[LLVMdev] codeGen, instruction write one value to the input register.
Tks Cameron,
I did some study on it.
Now I am having the same problem as mentioned in this thread;"http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-January/057654.html” ,
> Looking at the X86 back-end code, it looks like there do exist
> multi-output instructions, but they all use physical (implicit) registers
> for the second destination, not arbitrary register types. And if I