search for: btsq

.... There is, however, a potential optimisation here for someone who knows their inline asm. Currently "set_bit(63, addr)" will use the "r" version of the constraint even on amd64 targets, materialising 63 with a "movl". With sufficiently clever faff, it could use "btsq" instead. Cheers. Tim.

Hi guys, I am trying to compile some files using clang + llvm and I am encountering the following error during the linking step: <inline asm>:1:2: error: ambiguous instructions require an explicit suffix (could be 'btsw', 'btsl', or 'btsq') bts $14,(%eax) Which basically does not make any sense, because I don't have the mentioned inline assembly in any of the C files, and furthermore even if I did, that is completely valid inline assembly (BTS as per x86 assembly reference does not need w,l or q modifiers) N.B.: T...

...thing Yes it does. > btrl $1, 0 > btr $1, 0 > btsl $1, 0 > bts $1, 0 What the heck is that supposed to show? It shows nothing at all. With an argument of '1', *of*course* gas will use "btsl", since that's the short form. Using the rex-predix and a btsq would be *stupid*. So gas will pick the appropriate form, exactly as claimed. Try some actual relevant test instead: bt %eax,mem bt %rax,mem and notice how they are actually fundamentally different. Test-case: int main(int argc, char **argv) { asm("bt %1,%0":"=m" (*...

...(in particular, it might well make users go "this is an array of 64-bit entities, so I should use btq", even though that is actually incorrect). Now, I obviously think that the user should have the choice to *override* the default thing, so sometimes you might have /* We use a 64-bit btsq to encourage the CPU to do it as a 64-bit read-modify-write, since we will do a 64-bit read of the result later, and otherwise we'll get a partial write buffer stall */ btsq $63, mem and then the assembler had obviously better use the size information the user gave it. But the thing is, th...

...ed from source and the latest llvm-gcc binaries for Linux x86_64. This code worked just fine with older versions of llvm-gcc on 32 bit Linux. FD_ZERO is defined in /usr/include/bits/select.h like this: # if __WORDSIZE == 64 # define __FD_ZERO_STOS "stosq" # define __FD_SET_BTS "btsq" # define __FD_CLR_BTR "btrq" # define __FD_ISSET_BT "btq" # else # define __FD_ZERO_STOS "stosl" # define __FD_SET_BTS "btsl" # define __FD_CLR_BTR "btrl" # define __FD_ISSET_BT "btl" # endif # define __FD_ZERO(fdsp) \ do {...

On Nov 20, 2013, at 10:04 AM, Ghitulete Razvan <razvan.ghitulete at gmail.com> wrote: > <inline asm>:1:2: error: ambiguous instructions require an explicit > suffix (could be 'btsw', 'btsl', or 'btsq') > bts $14,(%eax) This has come up before <https://groups.google.com/forum/#!topic/llvm-dev/vomnIQjefzA>. I don't recall if there was a resolution. -- Stephen Checkoway

...1, 0 in.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'btrw', 'btrl', or 'btrq') btr $1, 0 ^ btsl $1, 0 in.s:4:1: error: ambiguous instructions require an explicit suffix (could be 'btsw', 'btsl', or 'btsq') bts $1, 0 ^ Obviously, I misunderstood something major and screwed up the commit message. > int main(int argc, char **argv) > { > asm("bt %1,%0":"=m" (**argv): "a" (argc)); > asm("bt %1,%0":"=m" (**argv): "a" ((...

1c54d77 (x86: partial unification of asm-x86/bitops.h, 2008-01-30) changed a bunch of btrl/btsl instructions to btr/bts, with the following justification: The inline assembly for the bit operations has been changed to remove explicit sizing hints on the instructions, so the assembler will pick the appropriate instruction forms depending on the architecture and the context. Unfortunately,

...* + * Enable single-stepping and execute IRET. When IRET is + * finished the resulting #DB exception will cause a #VC + * exception to be raised. The #VC exception handler will send a + * NMI-complete message to the hypervisor to re-open the NMI + * window. + */ +sev_es_iret_kernel: + pushf + btsq $X86_EFLAGS_TF_BIT, (%rsp) + popf + iretq +SYM_CODE_END(sev_es_iret_user) +#endif + #ifndef CONFIG_IA32_EMULATION /* * This handles SYSCALL from 32-bit code. There is no way to program diff --git a/arch/x86/include/asm/sev-es.h b/arch/x86/include/asm/sev-es.h index a4d7574c5c6a..22f45782149e 1...

...p_64: * reload the page tables here. */ +#ifdef CONFIG_PARAVIRT + /* a CS ended in 0x3 indicates we're in userspace. That's where + * our paravirt guests run. */ + movq %cs, %rax + testq $0x3, %rax + jnz startup_paravirt +#endif + /* Enable PAE mode and PGE */ xorq %rax, %rax btsq $5, %rax @@ -208,10 +223,11 @@ ENTRY(early_idt_handler) cmpl $2,early_recursion_flag(%rip) jz 1f incl early_recursion_flag(%rip) - xorl %eax,%eax movq 8(%rsp),%rsi # get rip movq (%rsp),%rdx - movq %cr2,%rcx + GET_CR2_INTO_RAX + movq %rax,%rcx + xorq %rax, %rax leaq early_idt_msg(%rip)...

...p_64: * reload the page tables here. */ +#ifdef CONFIG_PARAVIRT + /* a CS ended in 0x3 indicates we're in userspace. That's where + * our paravirt guests run. */ + movq %cs, %rax + testq $0x3, %rax + jnz startup_paravirt +#endif + /* Enable PAE mode and PGE */ xorq %rax, %rax btsq $5, %rax @@ -208,10 +223,11 @@ ENTRY(early_idt_handler) cmpl $2,early_recursion_flag(%rip) jz 1f incl early_recursion_flag(%rip) - xorl %eax,%eax movq 8(%rsp),%rsi # get rip movq (%rsp),%rdx - movq %cr2,%rcx + GET_CR2_INTO_RAX + movq %rax,%rcx + xorq %rax, %rax leaq early_idt_msg(%rip)...

...p_64: * reload the page tables here. */ +#ifdef CONFIG_PARAVIRT + /* a CS ended in 0x3 indicates we're in userspace. That's where + * our paravirt guests run. */ + movq %cs, %rax + testq $0x3, %rax + jnz startup_paravirt +#endif + /* Enable PAE mode and PGE */ xorq %rax, %rax btsq $5, %rax @@ -208,10 +223,11 @@ ENTRY(early_idt_handler) cmpl $2,early_recursion_flag(%rip) jz 1f incl early_recursion_flag(%rip) - xorl %eax,%eax movq 8(%rsp),%rsi # get rip movq (%rsp),%rdx - movq %cr2,%rcx + GET_CR2_INTO_RAX + movq %rax,%rcx + xorq %rax, %rax leaq early_idt_msg(%rip)...

...p_64: * reload the page tables here. */ +#ifdef CONFIG_PARAVIRT + /* a CS ended in 0x3 indicates we're in userspace. That's where + * our paravirt guests run. */ + movq %cs, %rax + testq $0x3, %rax + jnz startup_paravirt +#endif + /* Enable PAE mode and PGE */ xorq %rax, %rax btsq $5, %rax @@ -208,10 +223,11 @@ ENTRY(early_idt_handler) cmpl $2,early_recursion_flag(%rip) jz 1f incl early_recursion_flag(%rip) - xorl %eax,%eax movq 8(%rsp),%rsi # get rip movq (%rsp),%rdx - movq %cr2,%rcx + GET_CR2_INTO_RAX + movq %rax,%rcx + xorq %rax, %rax leaq early_idt_msg(%rip)...

I cleaned up the top level makefile in the tools directory. No major changes. Except I have it so that ioemmu is compiled only with x86_32. Signed-off-by: Jerone Young <jyoung5@us.ibm.com> --- tools/Makefile.orig 2005-03-17 21:03:44.000000000 -0600 +++ tools/Makefile 2005-03-22 15:05:20.000000000 -0600 @@ -1,37 +1,33 @@ +XEN_ROOT = ../ +include $(XEN_ROOT)/tools/Rules.mk -all: -

Hi, here is the first public post of the patch-set to enable Linux to run under SEV-ES enabled hypervisors. The code is mostly feature-complete, but there are still a couple of bugs to fix. Nevertheless, given the size of the patch-set, I think it is about time to ask for initial feedback of the changes that come with it. To better understand the code here is a quick explanation of SEV-ES first.

Hi, here is the first public post of the patch-set to enable Linux to run under SEV-ES enabled hypervisors. The code is mostly feature-complete, but there are still a couple of bugs to fix. Nevertheless, given the size of the patch-set, I think it is about time to ask for initial feedback of the changes that come with it. To better understand the code here is a quick explanation of SEV-ES first.