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Dear all, Considering this simple example of hexbinplot: mixdata <- data.frame(x = c(rnorm(5000), rnorm(5000,4,1.5)), y = c(rnorm(5000), rnorm(5000,2,3)), a = gl(2, 5000)) fig <- hexbinplot(y ~ x | a, mixdata) print(fig) update(fig, colramp = BTC) produces a bad (non-updated) legend. Compare it with: hexbinplot(y ~ x | a, mixdata, colramp = BTC) What should I do to update the plot with the correct legend? (I'm using R 2.10.1 under Windows XP). Thanks in advance, Marcin

I will be out of the office starting 2005-08-05 and will not return until 2005-08-22. I will respond to your message when I return.However you can contact me in kumar.pn@gmail.com ,Mobile (0)9848580960

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> The compare of interest is clear, I think. It compares a Vector Induction Variable with a broadcasted loop invariant value, aka the BTC. Obtaining the latter operand is the goal, clearly, but to do so, the former operand needs to be recognized as a VIV. Yep, exactly that. > What if this compare is not generated by LV’s fold-tail-by-masking transformation? Not sure I completely follow this, because the whole point is that @llv...

..."com32: add a centralized bitops header" This reverts part of commit db74cf6c4182f40ecf7fad1f04799d09d82f896d. The usage of the centralized bitops in com32/lib/vsscanf.c is not correct because the bitmap that we're accessing is too large for the 'bt', 'bts' and 'btc' instructions to operate on, i.e. the instructions cannot address all the bits of the bitmap as the size of 'matchmap' is 32 bytes. This commit doesn't entirely revert db74cf6 as having centralised bitops does make sense in principle, it's just that we can't use it in vssca...

...instruction, it is difficult to imagine for me at this point that being unable to analyse this icmp would cripple things. > Could you elaborate on these more complicated cases and the difficulty they entail? The problem that we are solving is that we need the scalar loop backedge taken count (BTC), or just the iteration count, of the original scalar loop for a given vector loop. Just to be clear, we do not only need the vector iteration count, but again also the scalar loop Iteration Count (IC). We need this for a certain form of predication. This information, the scalar loop IC is produced...

...ead of TEST. Previously, TEST was always used for bits 0-31 and BT was always used for bits 32-63. Since the BT instruction is 16b smaller than TEST for the bits 8-31 case, 32b vs 48b, and not irredeemably slower, it makes sense to use BT in cases where size matters. Similar logic is possible for BTC and BTS. However, LowerToBTC and LowerToBTS would need to be written and used and that's a larger patch. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150124/9f79c1dc/attachment.html> --------------...

Ok. To go back to the original issue, would it be meaningful to add a SCEVUMax(0, BTC) on the final BTC computed by SCEV? So that it does not use "negative values"? On Wed, Aug 15, 2018 at 2:40 PM Friedman, Eli <efriedma at codeaurora.org> wrote: > On 8/15/2018 2:27 PM, Alexandre Isoard wrote: > > I'm not sure I understand the poison/undef/UB distinct...

...up. > > In case you have missed this, this is not LKML. Please keep your abusive > language at home. Linus and hpa are no almighty authorities here and > this is not the Linux kernel community. > Linus is an expert on the x86 instruction set, so his advice on what to do with bts and btc should be taken seriously. So i thing that although Linus is not an LLVM authority, he should be considered an x86 authority. James. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130717/e08cc207/attachment...

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Asic-technologies.com 9.3-9.9 GHash/sec 6 Board (has 48 chips) - 30 BTC - $3000 USD This unit will make: Coins per 24h at these conditions 0.2965 BTC Revenue per day29.08 USD Each module board uses about 31 Watts of power. Mining board's supplied , Case, power supply , On-board heat sink , USB connectors. Ready assembled All the boards are linked together , With...

Asic-technologies.com We make ASIC Bitcoin Mining Gear using the ASIC chips Sourced from Taiwan. 3.1 -3.3 GHash/sec 4 Board (has 32 chips) - 15 BTC 9.3-9.9 GHash/sec 12 Board (has 96 chips) - 30 BTC Each module board uses about 39 Watts of power. Mining board's supplied (No case) power supply , On-board heat sink , USB connectors. Ready assembled (suggest that you insert board's into a case and add cooling fans) All the boards are link...

Hey everybody, I've been using mysql databases more and more. I've run across a couple of instances where I've either made a mistake on the ip address of the mysql database or for whatever reason, mysql wasn't running. In those instances, I've noted that the mysql command will hang indefinitely (I've counted to 40 before killing it). The offending line is: exten =>

...e memory access size. The SDM entry for BT mentions that the instruction may touch 2 or 4 bytes depending on the operand size, but doesn't specifically mention that a 64 bit operation size touches 8 bytes - and it doesn't mention anything at all about operand size and access size in BTR/BTS/BTC (unless it's implied as part of the discussion about encoding the MSBs of a constant bit offset in the offset of the addressing mode). Is that an oversight? > The > access size generally is meaningless from a semantic standpoint > (little-endian being the only sane model), but the ac...

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On Sun, Jul 14, 2013 at 5:56 AM, Ramkumar Ramachandra <artagnon at gmail.com> wrote: > 1c54d77 (x86: partial unification of asm-x86/bitops.h, 2008-01-30) > changed a bunch of btrl/btsl instructions to btr/bts, with the following > justification: > > The inline assembly for the bit operations has been changed to remove > explicit sizing hints on the instructions, so the

...hat said, I have never run experiments to verify that > such instructions are critical to kernel performance. I was trying to keep the set of operations as small as possible. Supporting all of the bitwise operations on the x86 architecture would be very difficult due to their number. (BTS, BTR, BTC...) Several of these also have no easy emulation available for other architectures. (Imagine doing an atomic test and set of a single bit, without affecting the rest of the bits, on SPARC..) Others do not fit well into the SSA representation of LLVM. This is particularly true of the non-exchanging...

On Wed, Jul 17, 2013 at 11:54:21AM +0530, Ramkumar Ramachandra wrote: > Jim Grosbach wrote: > > No. The above rule is absolutely the wrong thing to do, as has been > > previously noted. > > I don't give a shit about whether you think it is "absolutely wrong" > or not; I did what hpa and the Intel manual outlined. If you have > some _reason_ not to do

...r bits 0-31 and BT was always used for bits 32-63. > > > > Since the BT instruction is 16b smaller than TEST for the bits 8-31 > case, 32b vs 48b, and not irredeemably slower, it makes sense to use BT in > cases where size matters. > > > > Similar logic is possible for BTC and BTS. However, LowerToBTC and > LowerToBTS would need to be written and used and that's a larger patch. > > <pat><tst64.c>_______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.u...