search for: bsp

...84 [1] Modules linked in: Pid: 221, CPU 3, comm: khelper psr : 00001010085a2010 ifs : 8000000000000813 ip : [<a0000001005fed30>] Not tainted ip is at sba_alloc_range+0x50/0x1280 unat: 0000000000000000 pfs : 0000000000000814 rsc : 0000000000000003 rnat: 0000000000000000 bsps: 0000000000000000 pr : 0000000000065995 ldrs: 0000000000000000 ccv : 0000000000000000 fpsr: 0009804c8a70033f csd : 0000000000000000 ssd : 0000000000000000 b0 : a000000100600f80 b6 : a000000100308d00 b7 : a00000010055e3a0 f6 : 1003e6db6db6db6db6db7 f7 : 1003e000000000000f763 f8 : 100059...

...be possible to have asterisk spoof the User-Agent field and register itself? Any thoughts/feedback? Thanks. > > No. Time Source Destination Protocol Info > 222 53.601179 172.21.5.102 216.115.25.187 SIP Request: REGISTER sip:bspgroup1.bsp.vonage.net:5061 > > Frame 222 (622 bytes on wire, 622 bytes captured) > Ethernet II, Src: 00:0f:9f:86:42:d4, Dst: 00:06:25:db:aa:25 > Internet Protocol, Src Addr: 172.21.5.102 (172.21.5.102), Dst Addr: 216.115.25.187 (216.115.25.187) > User Datagram Protocol, Src Port: 5061...

...in: Pid: 14, CPU 0, comm: xenwatch psr : 0000101008422010 ifs : 8000000000000307 ip : [<a0000001004c2ca0>] Not tainted (2.6.26-rc4xen-ia64-dirty) ip is at dev_kfree_skb_irq+0x20/0x1a0 unat: 0000000000000000 pfs : 400000000000040b rsc : 0000000000000007 rnat: 0000000000000000 bsps: 0000000000000000 pr : 000000000000a941 ldrs: 0000000000000000 ccv : 0000000000000000 fpsr: 0009804c8a70433f csd : 0000000000000000 ssd : 0000000000000000 b0 : a0000001003efb70 b6 : a000000100070e40 b7 : a000000100070e40 f6 : 1003e000000fcb75352b1 f7 : 1003e000000000014ff97 f8 : 1003e00fcb7...

...in: Pid: 14, CPU 0, comm: xenwatch psr : 0000101008422010 ifs : 8000000000000307 ip : [<a0000001004c2ca0>] Not tainted (2.6.26-rc4xen-ia64-dirty) ip is at dev_kfree_skb_irq+0x20/0x1a0 unat: 0000000000000000 pfs : 400000000000040b rsc : 0000000000000007 rnat: 0000000000000000 bsps: 0000000000000000 pr : 000000000000a941 ldrs: 0000000000000000 ccv : 0000000000000000 fpsr: 0009804c8a70433f csd : 0000000000000000 ssd : 0000000000000000 b0 : a0000001003efb70 b6 : a000000100070e40 b7 : a000000100070e40 f6 : 1003e000000fcb75352b1 f7 : 1003e000000000014ff97 f8 : 1003e00fcb7...

...in: Pid: 14, CPU 0, comm: xenwatch psr : 0000101008422010 ifs : 8000000000000307 ip : [<a0000001004c2ca0>] Not tainted (2.6.26-rc4xen-ia64-dirty) ip is at dev_kfree_skb_irq+0x20/0x1a0 unat: 0000000000000000 pfs : 400000000000040b rsc : 0000000000000007 rnat: 0000000000000000 bsps: 0000000000000000 pr : 000000000000a941 ldrs: 0000000000000000 ccv : 0000000000000000 fpsr: 0009804c8a70433f csd : 0000000000000000 ssd : 0000000000000000 b0 : a0000001003efb70 b6 : a000000100070e40 b7 : a000000100070e40 f6 : 1003e000000fcb75352b1 f7 : 1003e000000000014ff97 f8 : 1003e00fcb7...

G92's seem to require some additional bit of initialization before the BSP engine can work. It feels like clocks are not set up for the underlying VLD engine, which means that all commands submitted to the xtensa chip end up hanging. VP seems to work fine though. This still allows people to force-enable the bsp engine if they want to play around with it, but makes it har...

These chipsets include the VP2 engine which is composed of a bitstream processor (BSP) that decodes H.264 and a video processor (VP) which can do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are driven by separate xtensa chips embedded in the hardware. This patch provides the mechanism to load the kernel for the xtensa chips and provide the necessary interactions to...

Hi Alex: I was looking at an ia64 bug report and noticed that we don''t actually free IRQs in the free_irq_vector hypercall. This would eventually lead to alloc_irq_vector failing. Unless I''m mistaken something like calling pci_disable_device and pci_enable_device can lead to this situation. So I''m wondering what the original problem was and how could we resolve it

These chipsets include the VP2 engine which is composed of a bitstream processor (BSP) that decodes H.264 and a video processor (VP) which can do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are driven by separate xtensa chips embedded in the hardware. This patch provides the mechanism to load the kernel for the xtensa chips and provide the necessary interactions to...

For NV98+, BSP/VP/PPP are all FUC-based engines. Hook them all up in the same way as NVC0, but with a couple of different values. Also make sure that the PPP engine is handled in the fifo/mc/vm. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- It seems like VP4.0 is basically working here... only...

On Mon, Jun 3, 2013 at 5:02 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > These chipsets include the VP2 engine which is composed of a bitstream > processor (BSP) that decodes H.264 and a video processor (VP) which can > do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are > driven by separate xtensa chips embedded in the hardware. This patch > provides the mechanism to load the kernel for the xtensa chips and > provide the necess...

Hey, Op 04-06-13 20:38, Ilia Mirkin schreef: > On Mon, Jun 3, 2013 at 5:02 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: >> These chipsets include the VP2 engine which is composed of a bitstream >> processor (BSP) that decodes H.264 and a video processor (VP) which can >> do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are >> driven by separate xtensa chips embedded in the hardware. This patch >> provides the mechanism to load the kernel for the xtensa chips and >> pr...

...n.lankhorst at canonical.com> wrote: > Hey, > > Op 04-06-13 20:38, Ilia Mirkin schreef: >> On Mon, Jun 3, 2013 at 5:02 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: >>> These chipsets include the VP2 engine which is composed of a bitstream >>> processor (BSP) that decodes H.264 and a video processor (VP) which can >>> do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are >>> driven by separate xtensa chips embedded in the hardware. This patch >>> provides the mechanism to load the kernel for the xtensa chips and...

...00000041c0000 vcpu 0 >(XEN) >(XEN) CPU 1 >(XEN) psr : 0000101008222018 ifs : 8000000000000a98 ip : >[<f0000000040375a0>] >(XEN) ip is at csched_schedule+0x970/0xf70 >(XEN) unat: 0000000000000000 pfs : 0000000000000a98 rsc : 0000000000000003 >(XEN) rnat: 0000121008226018 bsps: f00000000405a6c0 pr : 000000000001aaa9 >(XEN) ldrs: 0000000000000000 ccv : 0000000000000000 fpsr: 0009804c8a70033f >(XEN) csd : 0000000000000000 ssd : 0000000000000000 >(XEN) b0 : f0000000040375a0 b6 : f000000004049c80 b7 : e000000000100800 >(XEN) f6 : 0fffbccccccccc8c00000 f7 :...

...764837839, 1.00770187223770, 0.780805622450771, 0.585650849661306, 0.421553364080296, 0.287358347766713, 0.18150469048976, 0.102094654969619 ) plot(d2,r2,type="b") require(splines) sp <- interpSpline(r2,d2) psp <- predict(sp) points(psp$y,psp$x,col=5) bsp <- backSpline(sp) lines(predict(bsp,seq(0,6,length=101)),col=2) The prediction from the spline (cyan dots) looks perfectly reasonable. The prediction from the inverted spline matches the curve over part of the range but goes crazy elsewhere. I would have expected it to be reasonably close...

only BSP can really do clear_all_shadow_status. This fixes SMP IA32 VMX guest booting on IA32 xen. Signed-off-by: Xin Li <xin.b.li@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

On 15 Apr 2006, at 15:54, Li, Xin B wrote: > only BSP can really do clear_all_shadow_status. > This fixes SMP IA32 VMX guest booting on IA32 xen. Why can only VCPU0 do this? Is the argument to clear_all_shadow_status() always current domain? If so that should probably be asserted, or the argument removed. -- Keir ___________________________...

...pe_video_profile profile) +{ + struct nouveau_screen *screen = nouveau_screen(pscreen); + int chipset = screen->device->chipset; + int vp3 = chipset < 0xa3 || chipset == 0xaa || chipset == 0xac; + int vp5 = chipset >= 0xd0; + int ret; + + /* For all chipsets, try to create a BSP objects. Assume that if firmware + * is present for it, firmware is also present for VP/PPP */ + if (!(screen->firmware_info.profiles_checked & 1)) { + struct nouveau_object *bsp = NULL; + int oclass; + if (chipset < 0xc0) + oclass = 0x85b1; + else if (vp5...

Recently, I ran rsync and got the following message: skipping non-regular file "981005_plteph-de405s.bsp" It turns out that the file in question is really a degenerate link that points back to itself. lrwxr-xr-x 1 18450 other 24 May 9 20:38 981005_plteph-de405s.bsp -> 981005_PLTEPH-DE405S.bsp The confusing this is that although rsync printed what looks like an error, it sti...

https://bugs.freedesktop.org/show_bug.cgi?id=95330 Bug ID: 95330 Summary: [NV84] Hangs with gr: DATA_ERROR [INVALID_BITFIELD], TRAP_PROP [RT_FAULT], fb: trapped write [PGRAPH] [PROP] [RT0] [PAGE_NOT_PRESENT], bsp: Watchdog interrupt, engine hung Product: xorg Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assignee: nouvea...