search for: brucehoult

...k you again for your time and responses. If I have inadvertently been rude, please forgive someone new to LLVM? And if your forgiveness stretches that far, perhaps you could clue me on just how I was rude so that I can avoid it in the future? More thanks, JD Jones From: Bruce Hoult [mailto:brucehoult at sifive.com] Sent: Friday, December 14, 2018 1:29 PM To: jjones at prc-hsv.com Cc: LLVM Developers Mailing List <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] LLVM Backend for a platform with no (normal) stack Having your function prologue call malloc() and epilogue call free() (...

...? Thank you again for your time and responses. If I have inadvertently been rude, please forgive someone new to LLVM? And if your forgiveness stretches that far, perhaps you could clue me on just how I was rude so that I can avoid it in the future? More thanks, JD Jones From: Bruce Hoult [mailto:brucehoult at sifive.com<mailto:brucehoult at sifive.com>] Sent: Friday, December 14, 2018 1:29 PM To: jjones at prc-hsv.com<mailto:jjones at prc-hsv.com> Cc: LLVM Developers Mailing List <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> Subject: Re: [llvm-dev] LLVM Backe...

Thanks for your response. Please see below. From: Bruce Hoult [mailto:brucehoult at sifive.com] Sent: Thursday, December 13, 2018 5:58 PM To: jjones at prc-hsv.com Cc: LLVM Developers Mailing List <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] LLVM Backend for a platform with no (normal) stack Do you have a register that you can store a memory address >>...

On Tue, 19 Jun 2018 at 20:46, Bruce Hoult <brucehoult at sifive.com> wrote: > Furthermore .. in the articles you reference, the -DCLS=$(getconf LEVEL1_DCACHE_LINESIZE) is passed when compiling the user's program -- one doing extensive blocked matrix operations -- and not when building the *compiler*. It's worse. At least in the first ca...

...s possible though that someone is using clang as the assembler driver and we'd pass through -mthumb when they weren't expecting it. Peter On Thu, 15 Nov 2018 at 12:39, Tim Northover via cfe-dev <cfe-dev at lists.llvm.org> wrote: > > On Thu, 15 Nov 2018 at 12:25, Bruce Hoult <brucehoult at sifive.com> wrote: > > OK, I just checked, and -mcpu=cortex-{m3,m4,m7,a7,a9,a15,a53} gives Thumb at -O1, -O1, -Os on the following gcc: > > If anything I'd be inclined to just default to Thumb always. I haven't > checked myself, but rumour has it the icache benefits mak...

...clang as the assembler driver and we'd pass through -mthumb when they weren't expecting it. Peter On Thu, 15 Nov 2018 at 12:39, Tim Northover via cfe-dev <cfe-dev at lists.llvm.org<mailto:cfe-dev at lists.llvm.org>> wrote: > > On Thu, 15 Nov 2018 at 12:25, Bruce Hoult <brucehoult at sifive.com<mailto:brucehoult at sifive.com>> wrote: > > OK, I just checked, and -mcpu=cortex-{m3,m4,m7,a7,a9,a15,a53} gives Thumb at -O1, -O1, -Os on the following gcc: > > If anything I'd be inclined to just default to Thumb always. I haven't > checked myself, bu...

I've never tried -mcpu=cortex-xyz but I know -march=armv7 defaults to Thumb OK, I just checked, and -mcpu=cortex-{m3,m4,m7,a7,a9,a15,a53} gives Thumb at -O1, -O1, -Os on the following gcc: arm-linux-gnueabihf-gcc (Ubuntu/Linaro 7.3.0-27ubuntu1~18.04) 7.3.0 cortex-m0 fails because it doesn't do hard float. I don't have an eabi compiler around. On Thu, Nov 15, 2018 at 4:14 AM, Tim

...hope. Searching the Altera (redirected to Intel) website on "LLVM" got no hits, reducing hope. More thanks than I can type, JD -----Original Message----- From: Anton Korobeynikov [mailto:anton at korobeynikov.info] Sent: Saturday, December 15, 2018 8:33 AM To: jjones at prc-hsv.com Cc: brucehoult at sifive.com; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] LLVM Backend for a platform with no (normal) stack Well, since you're having memory, then things are more or less doable – all you need is to create and maintain stack by yourself. This could be done on per-func...

July 15, 2019 1:16 PM, "Bruce Hoult" <brucehoult at sifive.com> wrote: > Take, for example, RISC-V. You have 32 registers that, in the base > fixed-length 32 bits long instruction set, are absolutely > interchangeable with each other. No instructions use implicit source > or destination registers, any register can be used for anyt...

Not only do FPGAs not support recursion, we don’t even support calls! All user code must be inlined into one kernel/component, which is then used to create HDL for the FPGA. Mark From: Bruce Hoult <brucehoult at sifive.com> Sent: December 17, 2018 9:28 AM To: Mendell, Mark P <mark.p.mendell at intel.com> Cc: jjones at prc-hsv.com; LLVM Developers Mailing List <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] LLVM Backend for a platform with no (normal) stack On Mon, Dec 17, 2018 at 6:...

Alex, ping? There was a thread about moving Risc-V out of experimental but I think it didn't go anywhere? Separately, do the listed patches sound okay for merging? Thanks, Hans On Fri, Jan 25, 2019 at 4:40 PM Bruce Hoult <brucehoult at sifive.com> wrote: > > In https://llvm.org/svn/llvm-project/llvm/branches/release_80 I find > that RISCV is still in LLVM_EXPERIMENTAL_TARGETS_TO_BUILD. not > LLVM_TARGETS_TO_BUILD. I thought people had agreed to change that in > this release? > > There are also at least...

On Fri, 16 Nov 2018 at 00:09, Bruce Hoult via llvm-dev <llvm-dev at lists.llvm.org> wrote: > The original svn has atomic commits across all projects. It would be crazy to use a git version that doesn't duplicate that. I thought someone found that only a tiny fraction of commits actually made use of that. It's definitely not something anyone can rely on, so I'd consider it

What percentage of performance advantage do you expect to get from having a basic block with 14000 instructions, rather than breaking it up a bit? On Wed, May 30, 2018 at 12:02 AM, David Jones via llvm-dev < llvm-dev at lists.llvm.org> wrote: > My back-end code generator uses LLVM 5.0.1 to optimize and generate code > for x86_64. > > If I run it on a given sample of IR, it

On Fri, 16 Nov 2018 at 00:35, Bruce Hoult <brucehoult at sifive.com> wrote: > Yes, I'd expect only a tiny fraction of commits to change the interface between say, clang and llvm in an incompatible way, but where they do it's essential to get both sides at the same time if you want to to have every commit buildable for things such as bise...

On Fri, Feb 1, 2019 at 1:19 AM Bruce Hoult <brucehoult at sifive.com> wrote: > On Thu, Jan 31, 2019 at 11:53 PM Luke Kenneth Casson Leighton via > llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > --- > > crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 > > > > On Thu, Jan 31, 2019...

Hello the list, What is the correct type for a global of size zero? I need the compiler to be able to generate one, so that the linker will insert it at a specific position without perturbing the location of anything else in the section. I have tried a zero-length array (generates something at least one byte). At Nuno’s suggestion, I tried a structure with no fields. In release builds, this

Hello All, I need some help with respect to cross compiling for ARM. While trying to cross compile for the ARM target, I am hitting some errors. I need some help in this. I use the following command to cross compile for ARM Cortex A72 (ARM v8-a), 64 bit architecture: *cmake -v CC='clang' CXX='clang++' -DCMAKE_C_COMPILER=../build_directory_llvm/bin/clang

Silly question .. what do you expect to do driving LLVM directly that you couldn't do by generating C and compiling that? It's a lot easier. On Tue, May 15, 2018 at 11:38 AM, Jason Ott via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Ok, so I can use the structure-type to represent base or acid or salts. > My next question is how union-typing works in LLVM. After reading

Dear Sir or Ma'am; I have found a wealth of help and information on writing an LLVM backend. And, my platform has no stack. Can you point me to any information that would specifically address creating a backend for this kind of platform? In previous wanderings, I thought I ran across a phrase "platforms with no stack such as FPGAs", but I can't find that mention, now.

Env vars that change compiler output make it impossible to write tools such as ccache or distcc. Including the entire env in the hash value that determines whether ccache has a cache hit (as well as the compiler command line and the preprocessed source file) would be ridiculous and would result in very few cache hits. On Thu, Sep 6, 2018 at 11:34 AM, Matthias Braun via llvm-dev < llvm-dev at