Displaying 6 results from an estimated 6 matches for "brr_uncond".
2014 Sep 05
3
[LLVMdev] [PATCH] [MachineSinking] Conservatively clear kill flags after coalescing.
...without clearing the kill flag:
BB#13: derived from LLVM BB %CF250
Predecessors according to CFG: BB#12 BB#13 BB#14
...
%vreg520<def> = COPY %vreg368
%vreg568<def,tied1> = cmp %vreg341<tied0>, %vreg520<kill>
brr_cond <BB#13>
brr_uncond <BB#14>
Successors according to CFG: BB#13, BB#14
Into
BB#13: derived from LLVM BB %CF250
Predecessors according to CFG: BB#12 BB#13 BB#14
...
%vreg568<def,tied1> = cmp %vreg341<tied0>, %vreg368<kill>
brr_cond <BB#13>
brr_uncon...
2014 Sep 05
5
[LLVMdev] [PATCH] [MachineSinking] Conservatively clear kill flags after coalescing.
...t;> Predecessors according to CFG: BB#12 BB#13 BB#14
>>> …
>>> %vreg520<def> = COPY %vreg368
>>> %vreg568<def,tied1> = cmp %vreg341<tied0>, %vreg520<kill>
>>> brr_cond <BB#13>
>>> brr_uncond <BB#14>
>>> Successors according to CFG: BB#13, BB#14
>>>
>>> Into
>>>
>>> BB#13: derived from LLVM BB %CF250
>>> Predecessors according to CFG: BB#12 BB#13 BB#14
>>> …
>>> %vreg568<def,tied...
2016 Mar 04
2
PHI node to different register class vs TailDuplication
...TailDuplication we have:
BB#2: derived from LLVM BB %bb2
Predecessors according to CFG: BB#1
%vreg12<def> = mv16Sym <ga:@a>; rN:%vreg12
%vreg13<def> = mv_nimm6_ar16 0; aNlh_rN:%vreg13
mv_ar16_r16_rmod1 %vreg13<kill>, %vreg12<kill>; aNlh_rN:%vreg13 rN:%vreg12
brr_uncond <BB#4>;
Successors according to CFG: BB#4(?%)
BB#4: derived from LLVM BB %bb4
Predecessors according to CFG: BB#2 BB#3
%vreg2<def> = PHI %vreg0, <BB#2>, %vreg1, <BB#3>; rN:%vreg2
aNlh_0_7:%vreg0 aNlh_rN:%vreg1
mv_a32_r16_rmod1 %vreg3, %vreg2; aN32_0_7:%vreg3 rN...
2015 Apr 17
2
[LLVMdev] Multiple connected components in live interval
..._u_u>
> %vreg45<def> = COPY %r0
> %vreg46<def> = COPY %r1
> %vreg3<def> = COPY %vreg46 <<<<<<<<<<<<<<<<<<
> ST %vreg46, %vreg0
> ST %vreg46, %vreg1
> brr_uncond <BB#4>
>
> Does this ring any bell? Could there be any place that misses something about the resulting LiveInterval due to a phys reg copy?
>
> thanks
>
> /Jonas
>
> PS Quentin, as I said I could not reproduce this error on any in-tree target.
Ah right.
>
>...
2015 Apr 20
2
[LLVMdev] Multiple connected components in live interval
...= COPY %r0
>>> %vreg46<def> = COPY %r1
>>> %vreg3<def> = COPY %vreg46 <<<<<<<<<<<<<<<<<<
>>> ST %vreg46, %vreg0
>>> ST %vreg46, %vreg1
>>> brr_uncond <BB#4>
>>>
>>> Does this ring any bell? Could there be any place that misses something about the resulting LiveInterval due to a phys reg copy?
>>>
>>> thanks
>>>
>>> /Jonas
>>>
>>> PS Quentin, as I said I could not r...
2015 Apr 16
2
[LLVMdev] Multiple connected components in live interval
Hi Jonas,
Could you file a PR with your test case please?
Thanks,
-Quentin
> On Apr 16, 2015, at 3:50 PM, Andrew Trick <atrick at apple.com> wrote:
>
>>
>> On Apr 16, 2015, at 6:58 AM, Jonas Paulsson <jonas.paulsson at ericsson.com <mailto:jonas.paulsson at ericsson.com>> wrote:
>>
>> Hi,
>>
>> I have come across a csmith generated