search for: breger

...jay Patel (spatel at rotateright.com) <spatel at rotateright.com>; Chandler Carruth (chandlerc at gmail.com) <chandlerc at gmail.com>; Quentin Colombet (qcolombet at apple.com) <qcolombet at apple.com>; Craig Topper (craig.topper at gmail.com) <craig.topper at gmail.com> Cc: Breger, Igor <igor.breger at intel.com> Subject: Re: GEP transformation by InstCombiner On 01/15/2018 12:21 PM, Demikhovsky, Elena wrote: Hi all, I'm working on an out-of-tree target and encountered the following problem: InstCombiner "normalizes" GEPs and extends Index operand to...

...right.com) > <spatel at rotateright.com>; Chandler Carruth (chandlerc at gmail.com) > <chandlerc at gmail.com>; Quentin Colombet (qcolombet at apple.com) > <qcolombet at apple.com>; Craig Topper (craig.topper at gmail.com) > <craig.topper at gmail.com> > *Cc:* Breger, Igor <igor.breger at intel.com> > *Subject:* Re: GEP transformation by InstCombiner > >   > >   > > On 01/15/2018 12:21 PM, Demikhovsky, Elena wrote: > > Hi all, > >   > > I’m working on an out-of-tree target and encountered the following &g...

...eir execution. Thanks, Zvi From: Hal Finkel [mailto:hfinkel at anl.gov] Sent: Saturday, June 24, 2017 05:17 To: hameeza ahmed <hahmed2305 at gmail.com>; llvm-dev at lists.llvm.org Cc: Demikhovsky, Elena <elena.demikhovsky at intel.com>; Rackover, Zvi <zvi.rackover at intel.com>; Breger, Igor <igor.breger at intel.com>; craig.topper at gmail.com Subject: Re: [llvm-dev] AVX Scheduling and Parallelism It is possible that the issue with scheduling is constrained due to pointer-aliasing assumptions. Could you share the source for the loop in question? RIP-relative indexing, a...

...*From:*Hal Finkel [mailto:hfinkel at anl.gov] > *Sent:* Saturday, June 24, 2017 05:17 > *To:* hameeza ahmed <hahmed2305 at gmail.com>; llvm-dev at lists.llvm.org > *Cc:* Demikhovsky, Elena <elena.demikhovsky at intel.com>; Rackover, Zvi > <zvi.rackover at intel.com>; Breger, Igor <igor.breger at intel.com>; > craig.topper at gmail.com > *Subject:* Re: [llvm-dev] AVX Scheduling and Parallelism > > It is possible that the issue with scheduling is constrained due to > pointer-aliasing assumptions. Could you share the source for the loop > in qu...

...on (-mtriple=i386-linux-gnu -mattr=+sse2 ) load i64, i64* %p1 - illegal, require narrowScalar action load double, double * %p1 - legal What is the best approach to Legalize this case ? Should I mark G_LOAD/G_STORE s64 as Custom? Regards, Igor Breger --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended...

...bal-isel-abort=2 simple_foo.ll Regards, Igor From: S. Bharadwaj Yadavalli [mailto:bharadwajy at gmail.com] Sent: Thursday, November 09, 2017 03:36 To: Aditya Nandakumar <proaditya at gmail.com> Cc: Craig Topper <craig.topper at gmail.com>; llvm-dev <llvm-dev at lists.llvm.org>; Breger, Igor <igor.breger at intel.com> Subject: Re: [llvm-dev] [GlobalISel] [X86] unable to legalize instruction Sorry for the late follow-up. Here is the output with the suggested option: $ llc -global-isel -pass-remarks-missed="gisel-*" simple_foo.ll LLVM ERROR: unable to legalize i...

Hi all, I'm working on an out-of-tree target and encountered the following problem: InstCombiner "normalizes" GEPs and extends Index operand to the Pointer width. It works fine if you can convert pointer to integer for address calculation and I assume that all registered targets do this. The target I'm working on has very restricted ISA for the

On 01/15/2018 12:21 PM, Demikhovsky, Elena wrote: > Hi all, >   > I’m working on an out-of-tree target and encountered the following > problem: >   > InstCombiner “normalizes” GEPs and extends Index operand to the > Pointer width. > It works fine if you can convert pointer to integer for address > calculation and I assume that all registered targets do this. >   >

....com) <spatel at rotateright.com>; Chandler Carruth (chandlerc at gmail.com) <chandlerc at gmail.com>; Hal Finkel (hfinkel at anl.gov) <hfinkel at anl.gov>; Quentin Colombet <qcolombet at apple.com>; Craig Topper (craig.topper at gmail.com) <craig.topper at gmail.com>; Breger, Igor <igor.breger at intel.com> Subject: Re: [llvm-dev] GEP transformation by InstCombiner > On 15 Jan 2018, at 18:21, Demikhovsky, Elena via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi all, > > I’m working on an out-of-tree target and encountered the follow...

> On 15 Jan 2018, at 18:21, Demikhovsky, Elena via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi all, > > I’m working on an out-of-tree target and encountered the following problem: > > InstCombiner “normalizes” GEPs and extends Index operand to the Pointer width. > It works fine if you can convert pointer to integer for address calculation and I assume

I believe if you pass(iirc) -pass-remarks-missed=“gisel-*”, it’ll print the instruction it failed to legalize. Sent from my iPhone > On Oct 11, 2017, at 6:44 PM, S. Bharadwaj Yadavalli via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Thanks for your quick reply. > > Here its is: > > =========== > > ; ModuleID = 'simple_foo.c' > source_filename

Hello, After generating AVX code for large no of iterations i came to realize that it still uses only 2 registers zmm0 and zmm1 when the loop urnroll factor=1024, i wonder if this register allocation allows operations in parallel? Also i know all the elements within a single vector instruction are computed in parallel but does the elements of multiple instructions computed in parallel? like are