Displaying 3 results from an estimated 3 matches for "branchresolv".
2007 Jan 11
1
[LLVMdev] Pattern matching questions
...> Yep, $$ should work.
>
> It doesn't. Here's the pattern:
>
> let isTerminator = 1, isBarrier = 1, noResults = 1 in {
> let isReturn = 1 in {
> def RET: BRForm<0b00010101100, (ops),
> "bi $$lr",
> BranchResolv,
> [(retflag)]>;
> }
> }
>
> Output from make:
>
> llvm[0]: Building SPU.td code emitter with tblgen
> tblgen: /work/scottm/llvm/utils/TableGen/CodeGenInstruction.h:118:
> std::pair<unsigned int, unsigned int>
> llvm::CodeGenInstructi...
2007 Jan 10
0
[LLVMdev] Pattern matching questions
...", "lr")).
>
>
> Yep, $$ should work.
It doesn't. Here's the pattern:
let isTerminator = 1, isBarrier = 1, noResults = 1 in {
let isReturn = 1 in {
def RET: BRForm<0b00010101100, (ops),
"bi $$lr",
BranchResolv,
[(retflag)]>;
}
}
Output from make:
llvm[0]: Building SPU.td code emitter with tblgen
tblgen: /work/scottm/llvm/utils/TableGen/CodeGenInstruction.h:118:
std::pair<unsigned int, unsigned int>
llvm::CodeGenInstruction::getSubOperandNumber(unsigned int) const:
Ass...
2007 Jan 09
2
[LLVMdev] Pattern matching questions
On Tue, 9 Jan 2007, Evan Cheng wrote:
>> - How does one deal with multiple instruction sequences in a pattern?
>> To load a constant is a two instruction sequence, but both
>> instructions only take two operands (assume that r3 is a 32-bit
>> register):
>>
>> ilhu $3, 45 # r3 = (45 << 16)
>> iohl $3, 5 # r3 |= 5