search for: bra

Displaying 20 results from an estimated 165 matches for "bra".

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2010 Jul 19
5
par("uin") ?
I inherited a function written either for an older version of R or SPlus to draw a brace, "{", in a graph. It uses par("uin") to determine the scaling of the quarter circles that make up segments of the brace, but that setting doesn't exist in current R. I'm guessing that, in the function below, ux, uy can be defined from par("usr") and par(&...
2005 Oct 14
2
Help with lattice, regressions and respective lines
# Dear R list, # # I'm needing help with lattice, regression and respective lines. # My data is below: bra = gl(2, 24, label = c('c', 's')) em = rep(gl(3, 8, label = c('po', 'pov', 'ce')), 2) tem = rep(c(0, 0, 30, 30, 60, 60, 90, 90), 6) tem2 = tem^2 r = rep(1:2, 24) y = c(40.58, 44.85, 32.55, 35.68, 64.86, 51.95, 42.52, 52.21, 40.58, 44.85, 3...
2009 Jun 21
0
[PATCH] nv50: initial support for IF, ELSE, ENDIF insns
...885,8 @@ emit_set(struct nv50_pc *pc, unsigned c_op, struct nv50_reg *dst, set_src_0(pc, dst, e); emit(pc, e); + pc->if_cond = e; + if (dst != rdst) free_temp(pc, dst); } @@ -1098,6 +1119,39 @@ emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask, } static void +emit_branch(struct nv50_pc *pc, int pred, unsigned cc, void *join) +{ + struct nv50_program_exec *e = exec(pc); + + if (join) { + set_long(pc, e); + e->inst[0] |= 0xa0000002; + emit(pc, e); + *(struct nv50_program_exec **)join = e; + e = exec(pc); + } + + set_long(pc, e); + e->inst[0] |= 0x100000...
2013 Mar 01
4
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...; add.f64 %fl3, %fl2, 0dBFF0000000000000; > > mov.f64 %fl2, 0d0000000000000000; > > mov.f64 %fl5, %fl2; > > mov.f64 %fl4, %fl2; > > bra.uni BB1_1; > > BB1_2: > > add.f64 %fl2, %fl2, 0d3FF0000000000000; > > sub.f64 %fl6, %fl6, %fl7; > > add.f64 %fl6, %fl6, %fl1; > > add.f64...
2014 Oct 24
3
[LLVMdev] IndVar widening in IndVarSimplify causing performance regression on GPU programs
...ed by NVPTX64) is: BB0_2: // =>This Inner Loop Header: Depth=1 mul.lo.s32 %r5, %r6, %r6; st.u32 [%rd4], %r5; add.s32 %r6, %r6, 3; add.s64 %rd4, %rd4, 12; setp.lt.s32 %p2, %r6, %r3; @%p2 bra BB0_2; in which %r6 is the induction variable i. With widening, the loop body becomes: BB0_2: // =>This Inner Loop Header: Depth=1 mul.lo.s64 %rd8, %rd10, %rd10; st.u32 [%rd9], %rd8; add.s64 %rd10, %rd10, 3;...
2007 Nov 27
2
exporting a split list
Using wk <- with(d, split(word, kind)), I get the following class table: wk$`1` [1] "a" "bra" ... # (*) wk$`10` "ca" "dabra" ... Now I need to export it in the following format: class num_members examples 1 23 a bra ... 10 4 ca dabra For each class C such as `1`, I need to print the number of m...
2014 May 01
13
[Bug 78161] New: [NV96] Artifacts in output of fragment program containing not unrolled loops with conditional break
https://bugs.freedesktop.org/show_bug.cgi?id=78161 Priority: medium Bug ID: 78161 Assignee: nouveau at lists.freedesktop.org Summary: [NV96] Artifacts in output of fragment program containing not unrolled loops with conditional break Severity: normal Classification: Unclassified OS: Linux (All)
2015 Aug 21
2
[CUDA/NVPTX] is inlining __syncthreads allowed?
...vcc sync.cu -arch=sm_35 -ptx gives // .globl _Z3foov .visible .entry _Z3foov( ) { .reg .pred %p<2>; .reg .s32 %r<3>; mov.u32 %r1, %tid.x; and.b32 %r2, %r1, 1; setp.eq.b32 %p1, %r2, 1; @!%p1 bra BB7_2; bra.uni BB7_1; BB7_1: bar.sync 0; bra.uni BB7_3; BB7_2: bar.sync 0; BB7_3: ret; } As you see, bar.sync is duplicated. On Fri, Aug 21, 2015 at 1:56 PM, Justin Holewinski <jholewinski at nvidia.com> wrote:...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...d.f64                                %fl3, %fl2, 0dBFF0000000000000; > > > mov.f64                                %fl2, 0d0000000000000000; > > > mov.f64                                %fl5, %fl2; > > > mov.f64                                %fl4, %fl2; > > > bra.uni                                BB1_1; > > > BB1_2: > > > add.f64                                %fl2, %fl2, 0d3FF0000000000000; > > > sub.f64                                %fl6, %fl6, %fl7; > > > add.f64                                %fl6, %fl6, %fl1; &...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...add.f64 %fl3, %fl2, 0dBFF0000000000000; >> > mov.f64 %fl2, 0d0000000000000000; >> > mov.f64 %fl5, %fl2; >> > mov.f64 %fl4, %fl2; >> > bra.uni BB1_1; >> > BB1_2: >> > add.f64 %fl2, %fl2, 0d3FF0000000000000; >> > sub.f64 %fl6, %fl6, %fl7; >> > add.f64 %fl6, %fl6, %fl1; >> >...
2013 Mar 01
1
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...%fl3, %fl2, > 0dBFF0000000000000; > >> > mov.f64 %fl2, 0d0000000000000000; > >> > mov.f64 %fl5, %fl2; > >> > mov.f64 %fl4, %fl2; > >> > bra.uni BB1_1; > >> > BB1_2: > >> > add.f64 %fl2, %fl2, > 0d3FF0000000000000; > >> > sub.f64 %fl6, %fl6, %fl7; > >> > add.f64 %fl6, %fl6, %f...
2015 May 04
4
imapc fetch optimization
Hi, On 05/04/15 10:59, Timo Sirainen wrote: > On 28 Apr 2015, at 23:49, Nagy, Attila <bra at fsn.hu> wrote: >> Hi, >> >> imapc does a lot of UID FETCH $UID (BODY.PEEK[]), which is nice, because it works even with the dumbest IMAP server, altough it really kills performance, especially on high latency lines. >> >> I wonder: if IMAP servers can effectively...
2013 Mar 01
2
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...2F_calc_2D_iteration_param_4; div.rn.f64 %fl2, %fl2, %fl3; add.f64 %fl2, %fl2, %fl2; add.f64 %fl3, %fl2, 0dBFF0000000000000; mov.f64 %fl2, 0d0000000000000000; mov.f64 %fl5, %fl2; mov.f64 %fl4, %fl2; bra.uni BB1_1; BB1_2: add.f64 %fl2, %fl2, 0d3FF0000000000000; sub.f64 %fl6, %fl6, %fl7; add.f64 %fl6, %fl6, %fl1; add.f64 %fl5, %fl5, %fl5; mul.f64 %fl4, %fl5, %fl4; add.f64 %fl4, %fl4, %fl3;...
2015 Jun 07
43
[Bug 90887] New: PhiMovesPass in register allocator broken
...above by computed value 6. return current position value or computed value (see if) The PhiMovesPass detects needNewElseBlock conditions and splits the 'else' edge incoming from the if thereby switching the order of incoming edges leading to adding copies from the sampled value to the if branch (discarding the computed values) and copies from the (unitialized) computed values to the new else block corrupting the result for all pixels except the ones where the condition is true (where it produces the originally sampled value). The fix slightly modifies the needNewElseBlock logic to not...
2014 Sep 04
10
MEMX improvements + DDR 2/3 MR generation
Patch 1 and 2 implement wait-for-vblank, required to remove flicker when reclocking memory Patch 3 and 4 allow me to do things between waiting for VBLANK and disabling FB, like pause PFIFO and wait for the engines to idle. This minimises the time PFIFO is paused, thus maximises performance. The rest of the patches speak for themselves. As the actual memory reclocking script is still somewhat prone
2016 Feb 08
2
RFC: HTTP based storage API
On 08 Feb 2016, at 12:56, Nagy, Attila <bra at fsn.hu> wrote: > > On 02/08/16 11:16, Timo Sirainen wrote: >> Oh, you were thinking about ability to provide IMAP/etc support for other random servers, and have Dovecot act as kind of a middleware and translate the requests. Maybe the answer is still jmap though? It would require...
2013 Mar 01
0
[LLVMdev] NVPTX CUDA_ERROR_NO_BINARY_FOR_GPU
...fl2, %fl2, %fl2; >聽 聽 聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl3, %fl2, 0dBFF0000000000000; >聽 聽 聽 聽 聽 聽 聽 聽 mov.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl2, 0d0000000000000000; >聽 聽 聽 聽 聽 聽 聽 聽 mov.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl5, %fl2; >聽 聽 聽 聽 聽 聽 聽 聽 mov.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl4, %fl2; >聽 聽 聽 聽 聽 聽 聽 聽 bra.uni聽 聽 聽 聽 聽 聽 聽 聽 BB1_1; > BB1_2: >聽 聽 聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl2, %fl2, 0d3FF0000000000000; >聽 聽 聽 聽 聽 聽 聽 聽 sub.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl6, %fl6, %fl7; >聽 聽 聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl6, %fl6, %fl1; >聽 聽 聽 聽 聽 聽 聽 聽 add.f64聽 聽 聽 聽 聽 聽 聽 聽 %fl5, %fl5,...
2012 Jun 29
0
Adding Bi-gram in the QueryParser and Object.
...ng list of terms. *Wild:* *Partial:* *Synonym:* **This is expanding which follow the pattern,synonym of term.It will pull out lot of similar terms and form a query with all those words.So considering this for bi-gram doesn't seem important.Please suggest if you feel it should be included. * * *BRA-KET: *These are bracketed expression.Currently the grammar have rule *BRA expr(E) KET* .so if there will be any scope of bi-grams in query inside BRA-KET it would have been consider while working on internal expression. * * *ValueRange: *No relation with Bi-grams. * * *Love: * *Hate: * Since we are...
2007 Sep 28
3
[LLVMdev] Crash on accessing deleted MBBs (new backend)
Hi, I'm trying to write up my little m68k backend things have been going smoothly. I've been working with the x86 backend as a template, fixing things as I go. Now I've run into branches and I have a crash I don't really understand. Here's the sample IR I'm running llc on to generate assembly: define i32 @ilog2(i32 %x) { entry: %tmp718 = icmp eq i32 %x, 0 ; <i1> [#uses=1] br i1 %tmp718, label %bb9, label %bb5 bb5: ; pr...
2017 Sep 11
2
Is it possible to disable pipelining in imapc?
On 09/11/2017 10:42 AM, Sami Ketola wrote: >> On 11 Sep 2017, at 11.24, Nagy, Attila <bra at fsn.hu> wrote: >> I use dovecot with a broken IMAP server (which doesn't properly implement command pipelining amongst others) as an imapc backend. >> Dovecot issues the above command sequence (SELECT and UID FETCH pipelined), which doesn't work with this server. >>...