search for: br_jtm

...nstrs' option from the MachineFunctionPass and I can see these instructions in the beginning of the passes *%vreg2<def> = MOVsi %vreg1, 18, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg2,%vreg1** **    %vreg3<def> = LEApcrelJT <jt#0>, pred:14, pred:%noreg; GPR:%vreg3** **    BR_JTm %vreg2<kill>, %vreg3<kill>, 0, <jt#0>; mem:LD4[JumpTable] GPR:%vreg2,%vreg3* and these at the end *%R0<def> = MOVsi %R0<kill>, 18, pred:14, pred:%noreg, opt:%noreg** **    %R1<def> = LEApcrelJT <jt#0>, pred:14, pred:%noreg** **    BR_JTm %R0<kill>,...

...odeEmitterGen.cpp, line 196: Case += " Value = " + PostEmitter + "(MI, Value);\n"; should be Case += " Value |= " + PostEmitter + "(MI, Value);\n"; This looks like it would affect all targets, except apparently only ARM uses this feature. 2) ARM BR_JTm and BR_JTadd do not emit because they were changed to PseudoInstructions but the ARMCodeEmitter wasn't updated to compensate. emitPseudoInstruction() asserts (llvm_unreachable). 3) FCONSTS/FCONSTD also assert similarly. emitMiscInstruciton which used to support these instructions was remov...

...ior. The some post-encoder hooks need to clear bits as well as set them. If you're seeing incorrect output from the post-encoder hook, it's because the hook itself has a bug. > This looks like it would affect all targets, except apparently only ARM uses this feature. > > 2) ARM BR_JTm and BR_JTadd do not emit because they were changed to PseudoInstructions but the ARMCodeEmitter wasn't updated to compensate. emitPseudoInstruction() asserts (llvm_unreachable). This is another symptom of the non-MC ARM JIT being unmaintained. It is correct for emitPseudoInstruction() to as...

...onst MachineInstr&MI, unsigned Val) const { return 0; } should instead be unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val) const { return Val; } >> This looks like it would affect all targets, except apparently only ARM uses this feature. >> >> 2) ARM BR_JTm and BR_JTadd do not emit because they were changed to PseudoInstructions but the ARMCodeEmitter wasn't updated to compensate. emitPseudoInstruction() asserts (llvm_unreachable). > > This is another symptom of the non-MC ARM JIT being unmaintained. It is correct for emitPseudoInstructi...

...(const MachineInstr&MI, unsigned Val) const { return 0; } should instead be unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val) const { return Val; } >> This looks like it would affect all targets, except apparently only ARM uses this feature. >> >> 2) ARM BR_JTm and BR_JTadd do not emit because they were changed to PseudoInstructions but the ARMCodeEmitter wasn't updated to compensate. emitPseudoInstruction() asserts (llvm_unreachable). > > This is another symptom of the non-MC ARM JIT being unmaintained. It is correct for emitPseudoInstructio...

...ned Val) const { return 0; } > should instead be > unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val) const { return Val; } > > >>> This looks like it would affect all targets, except apparently only ARM uses this feature. >>> >>> 2) ARM BR_JTm and BR_JTadd do not emit because they were changed to PseudoInstructions but the ARMCodeEmitter wasn't updated to compensate. emitPseudoInstruction() asserts (llvm_unreachable). >> >> This is another symptom of the non-MC ARM JIT being unmaintained. It is correct for emitPseudoI...

...+ // .long .LBB9_8 + // + // In pic mode the table entries are relative to table beginning + // requiring and extra addition + // + // The code generation logic for ARMISD::BR_JT will also + // emit the table (c.f. ARMAsmPrinter::printJTBlockOperand()) + // Also check "def BR_JTm" in ARMInstrInfo.td + + // allocate constant pool entry ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); - SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); - SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); - Table = DAG.ge...

On Jun 8, 2009, at 2:42 PM, robert muth wrote: > On Sun, Jun 7, 2009 at 11:53 PM, Evan Cheng <evan.cheng at apple.com> > wrote: >> >> On Jun 7, 2009, at 6:59 AM, robert muth wrote: >> >>> On Sat, Jun 6, 2009 at 4:51 PM, Evan Cheng<evan.cheng at apple.com> >>> wrote: >>>> +cl::opt<std::string>

On Sun, Jun 7, 2009 at 11:53 PM, Evan Cheng <evan.cheng at apple.com> wrote: > > On Jun 7, 2009, at 6:59 AM, robert muth wrote: > >> On Sat, Jun 6, 2009 at 4:51 PM, Evan Cheng<evan.cheng at apple.com> >> wrote: >>> +cl::opt<std::string> FlagJumpTableSection("jumptable-section", >>> +                                          

...+ // .long .LBB9_8 + // + // In pic mode the table entries are relative to table beginning + // requiring and extra addition + // + // The code generation logic for ARMISD::BR_JT will also + // emit the table (c.f. ARMAsmPrinter::printJTBlockOperand()) + // Also check "def BR_JTm" in ARMInstrInfo.td + + // allocate constant pool entry ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); - SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); - SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); - Table = DAG.ge...