search for: bqc

...add i32 %v1, %v2 > store i32 %v3, i32* %c > > maps to (using invented mnemonics): > > ASSIGN R0, %a > ASSIGN R1, %b > ASSIGN R2, %c > ADD *R2, *R0, *R1 > > Thanks. > > Regards, > Alex > > On 14 Oct 2016 1:00 p.m., "Alex Bradley" <alexbradley.bqc at gmail.com> > wrote: > >> >> > If I understand correctly: >> > >> > %v1 = load i32, i32* %a >> > %v2 = load i32, i32* %b >> > %v3 = add i32 %v1, %v2 >> > store i32 %v3, i32* %c >> > >> > maps to (using invented...

> If I understand correctly: > > %v1 = load i32, i32* %a > %v2 = load i32, i32* %b > %v3 = add i32 %v1, %v2 > store i32 %v3, i32* %c > > maps to (using invented mnemonics): > > ASSIGN R0, %a > ASSIGN R1, %b > ASSIGN R2, %c > ADD *R2, *R0, *R1 > > I.e. pattern > (store %c, (add (load %a), (load %b))) > becomes > (ADD (ASSIGN R2, %c), (ASSIGN

Hi All, I am new to llvm backend. I am trying out few examples to understand backend codegen. I have ported llvm LEG @ https://github.com/frasercrmck/llvm-leg to llvm 3.9 successfully. Currently, the LEG instructions are RISC load-store type instruction. I want to generate some instructions for register indirect mode, like following: IR: @a = local_unnamed_addr global i32 0, align 4 @b =

...lt;.P.......P. 6be0: 0d 0a 07 0a 0d 0a 14 0a 1e 0a 2d 0a 3c 0a 50 0a ..........-.<.P. 6bf0: 64 14 1e 5f 42 43 4d 01 a0 17 90 92 95 68 00 92 d.._BCM......h.. 6c00: 94 68 0a 64 41 49 4e 54 01 68 70 68 42 52 54 4c .h.dAINT.hphBRTL 6c10: 14 0c 5f 42 51 43 00 a4 5c 42 52 54 4c 5b 82 46 .._BQC..\BRTL[.F 6c20: 08 44 44 30 33 14 1d 5f 41 44 52 08 a0 0a 93 44 .DD03.._ADR....D 6c30: 49 44 33 00 a4 0a 03 a1 0b a4 7b 0b ff ff 44 49 ID3.......{...DI 6c40: 44 33 00 14 1c 5f 44 43 53 00 a0 0a 93 44 49 44 D3..._DCS....DID 6c50: 33 00 a4 0a 0b a1 0a a4 43 44 44 53 44 49 44 33 3.......CD...