Displaying 10 results from an estimated 10 matches for "bpfinstrinfo".
2017 Dec 03
2
5.0.1-rc2 has been tagged
...t<32>(imm32));
> BuildMI(BB, DL, TII.get(NewCC))
> .addReg(LHS)
> - .addImm(MI.getOperand(2).getImm())
> + .addImm(imm32)
> .addMBB(Copy1MBB);
> + }
>
> // Copy0MBB:
> // %FalseValue = ...
> diff --git a/lib/Target/BPF/BPFInstrInfo.td b/lib/Target/BPF/BPFInstrInfo.td
> index f683578..56f0f9c 100644
> --- a/lib/Target/BPF/BPFInstrInfo.td
> +++ b/lib/Target/BPF/BPFInstrInfo.td
> @@ -464,7 +464,7 @@ let usesCustomInserter = 1 in {
> (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm,
> GPR:$src, GPR...
2017 Nov 30
9
5.0.1-rc2 has been tagged
Hi,
I've tagged the 5.0.1-rc2 release, go ahead and start testing and report
your results.
-Tom
2016 Jan 07
3
BPF backend with vector operations - some strange error
...hen
building llc:
JEQ_ri: (BPFbrcc i64:i64:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$imm,
(imm:{i64:v4i32})<<P:Predicate_BPF_CC_EQ>>, (bb:Other):$BrDst)
Included from ~/LLVM/llvm38Nov2016/llvm/lib/Target/BPF/BPF.td:14:
~/LLVM/llvm38Nov2016/llvm/lib/Target/BPF/BPFInstrInfo.td:131:1: error: In JEQ_ri: Could
not infer all types in pattern!
defm JEQ : J<0x1, "jeq", BPF_CC_EQ>;
The error is a bit cryptic - basically it seems that we can have 2 different value
types (i64 and v4i32) for immediate operand imm. I guess this is because in
BPFRegis...
2020 May 12
2
BPF tablegen+codegen question
In BPF, an ADD instruction is defined as a 2 register instruction:
0x0f. add dst, src. dst += src
In BPFInstrInfo.td this kind of ALU instruction is defined with:
def _rr : ALU_RR<BPF_ALU64, Opc,
(outs GPR:$dst),
(ins GPR:$src2, GPR:$src),
"$dst "#OpcodeStr#" $src",
[(set GPR:$dst, (OpNode i64:$src2, i64...
2016 Oct 24
2
Instruction selection confusion at register - chooses vector register instead of scalar one
...wd), Addr:$addrdst)];
InstrItinClass Itinerary = itin;
string DecoderMethod = "DecodeMSA128Mem";
}
Also, BPF has its own scalar stores and loads (with the standard i64 registers), for
example (from https://github.com/llvm-mirror/llvm/blob/master/lib/Target/BPF/BPFInstrInfo.td):
class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
: STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
However, spills and loads with vector registers, created automatically at the border
of basic-blocks use the scalar stores and load...
2016 Oct 25
0
Instruction selection confusion at register - chooses vector register instead of scalar one
...$wd), Addr:$addrdst)];
InstrItinClass Itinerary = itin;
string DecoderMethod = "DecodeMSA128Mem";
}
Also, BPF has its own scalar stores and loads (with the standard i64 registers), for
example (from https://github.com/llvm-mirror/llvm/blob/master/lib/Target/BPF/BPFInstrInfo.td):
class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
: STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
However, spills and loads with vector registers, created automatically at the border
of basic-blocks use the scalar stores and loads...
2016 Jun 28
2
Instruction selection problem with type i64 - mistaken as v8i64?
...// %vector.body
ldd REGVEC0, -128(r10)
ldd r0, -48(r10)
I am surprised that the BPF scalar instructions ldd and std use vector register
REGVEC0, which have type v8i64.
For example, the TableGen definition of the LOAD instruction taken from
BPFInstrInfo.td is:
class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
: LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
So I am surprised that the instruction selector finds as match for operand i64:$dst
the vector register REGVEC0, whic...
2016 Jun 02
2
BPF backend with vector operations - error "Could not infer all types in, pattern!"
...ri: (BPFbrcc i64:i64:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$imm,
>> (imm:{i64:v4i32})<<P:Predicate_BPF_CC_EQ>>, (bb:Other):$BrDst)
>> Included from ~/LLVM/llvm38Nov2016/llvm/lib/Target/BPF/BPF.td:14:
>> ~/LLVM/llvm38Nov2016/llvm/lib/Target/BPF/BPFInstrInfo.td:131:1: error: In JEQ_ri: Could
>> not infer all types in pattern!
>> defm JEQ : J<0x1, "jeq", BPF_CC_EQ>;
>>
>>
>> The error is a bit cryptic - basically it seems that we can have 2 different value
>> types (i64 and v4i32) for immediate...
2017 Sep 18
0
[PATCH RFC 0/4] Initial 32-bit eBPF encoding support
...> Improve instruction encoding descriptions
> Improve class inheritance in instruction patterns
> New 32-bit register set
> Initial 32-bit ALU (BPF_ALU) encoding support in assembler
>
> lib/Target/BPF/BPFInstrFormats.td | 84 +++-
> lib/Target/BPF/BPFInstrInfo.td | 506 +++++++++++-------------
> lib/Target/BPF/BPFRegisterInfo.td | 74 +++-
> lib/Target/BPF/Disassembler/BPFDisassembler.cpp | 15 +
> test/MC/BPF/insn-unit-32.s | 53 +++
> 5 files changed, 427 insertions(+), 305 deletio...
2016 Jun 29
0
Instruction selection problem with type i64 - mistaken as v8i64?
...gt; ldd REGVEC0, -128(r10)
> ldd r0, -48(r10)
>
> I am surprised that the BPF scalar instructions ldd and std use vector
> register
> REGVEC0, which have type v8i64.
> For example, the TableGen definition of the LOAD instruction taken from
> BPFInstrInfo.td is:
> class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
> : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
>
> So I am surprised that the instruction selector finds as match for operand
> i64:$dst
> the...