search for: bpf_add

Displaying 4 results from an estimated 4 matches for "bpf_add".

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2020 May 12
2
BPF tablegen+codegen question
In BPF, an ADD instruction is defined as a 2 register instruction: 0x0f. add dst, src. dst += src In BPFInstrInfo.td this kind of ALU instruction is defined with: def _rr : ALU_RR<BPF_ALU64, Opc, (outs GPR:$dst), (ins GPR:$src2, GPR:$src), "$dst "#OpcodeStr#" $src", [(set
2017 Sep 18
0
[PATCH RFC 0/4] Initial 32-bit eBPF encoding support
...e so we could > construct 32-bit eBPF tests through hand-written assembly. > > A new 32-bit register set is introduced, its name is with "w" prefix and LLVM > assembler will encode statements like "w1 += w2" into the following 8-bit code > field: > > BPF_ADD | BPF_X | BPF_ALU > > BPF_ALU will be used instead of BPF_ALU64. > > NOTE, currently you can only use "w" register with ALU statements, not with > others like branches etc as they don't have different encoding for 32-bit > target. Great to see work in this direct...
2017 Sep 21
0
[iovisor-dev] [PATCH RFC 0/4] Initial 32-bit eBPF encoding support
...> > >    A new 32-bit register set is introduced, its name is with "w" > > > prefix and LLVM > > > assembler will encode statements like "w1 += w2" into the following > > > 8-bit code > > > field: > > > > > >      BPF_ADD | BPF_X | BPF_ALU > > > > > > BPF_ALU will be used instead of BPF_ALU64. > > > > > >    NOTE, currently you can only use "w" register with ALU > > > statements, not with > > > others like branches etc as they don't have different...
2017 Sep 23
0
[iovisor-dev] [PATCH RFC 0/4] Initial 32-bit eBPF encoding support
...; >> >>>>> prefix and LLVM >> >>>>> assembler will encode statements like "w1 += w2" into the following >> >>>>> 8-bit code >> >>>>> field: >> >>>>> >> >>>>> BPF_ADD | BPF_X | BPF_ALU >> >>>>> >> >>>>> BPF_ALU will be used instead of BPF_ALU64. >> >>>>> >> >>>>> NOTE, currently you can only use "w" register with ALU >> >>>>> statements, not wit...