Displaying 14 results from an estimated 14 matches for "boxptr".
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2012 Jul 27
1
[PATCH] nvc0: Add and enable vblank support
...X_CONFIG;
diff --git a/src/nv_proto.h b/src/nv_proto.h
index b546ebd..bcf927d 100644
--- a/src/nv_proto.h
+++ b/src/nv_proto.h
@@ -149,6 +149,7 @@ Bool NVAccelInit2D_NV50(ScrnInfoPtr pScrn);
Bool NVAccelInitNV50TCL(ScrnInfoPtr pScrn);
/* in nvc0_accel.c */
+void NVC0SyncToVBlank(PixmapPtr ppix, BoxPtr box);
Bool NVAccelInitM2MF_NVC0(ScrnInfoPtr pScrn);
Bool NVAccelInitCopy_NVC0(ScrnInfoPtr pScrn);
Bool NVAccelInitP2MF_NVE0(ScrnInfoPtr pScrn);
diff --git a/src/nv_type.h b/src/nv_type.h
index e1ea494..272e34f 100644
--- a/src/nv_type.h
+++ b/src/nv_type.h
@@ -102,6 +102,7 @@ typedef struct _NVR...
2012 Apr 15
1
[PATCH] nv50: fix crash in NV50SyncToVBlank
...om "WIP: port to new libdrm".
---
src/nv50_accel.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/nv50_accel.c b/src/nv50_accel.c
index 66d6cb8..7c640f2 100644
--- a/src/nv50_accel.c
+++ b/src/nv50_accel.c
@@ -44,6 +44,9 @@ NV50SyncToVBlank(PixmapPtr ppix, BoxPtr box)
if (!crtcs)
return;
+ if (!PUSH_SPACE(push, 10))
+ return;
+
BEGIN_NV04(push, SUBC_NVSW(0x0060), 2);
PUSH_DATA (push, pNv->vblank_sem->handle);
PUSH_DATA (push, 0);
--
1.7.8.5
2016 Oct 17
2
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...c0_xv.c
> @@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
> { dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
> };
> struct nouveau_pushbuf *push = pNv->pushbuf;
> - uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode << 18);
> float X1, X2, Y1, Y2;
> BoxPtr pbox;
> int nbox;
> @@ -105,71 +104,49 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
>
> PUSH_DATAu(push, pNv->scratch, TIC_OFFSET, 16);
> if (id == FOURCC_YV12 || id == FOURCC_I420) {
> - PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
> + PUSH_TIC(push, s...
2007 May 30
0
[PATCH] added comments
...ch
+ * @param dstBox
+ * @param x1
+ * @param y1
+ * @param x2
+ * @param y2
+ * @param width
+ * @param height
+ * @param src_w
+ * @param src_h
+ * @param drw_w
+ * @param drw_h
+ * @param clipBoxes
+ */
static void
NVPutOverlayImage(ScrnInfoPtr pScrnInfo, int offset, int id,
int dstPitch, BoxPtr dstBox,
@@ -358,6 +441,30 @@ extern Bool exaPixmapIsOffscreen(PixmapPtr p);
extern void exaMoveInPixmap(PixmapPtr pPixmap);
#endif
+/**
+ * NVPutBlitImage
+ * uses the DMA controller of the GPU to blit
+ * (block transfer) image from an offscreen buffer into
+ * the color buffer
+ *
+ * @param...
2019 Jan 21
5
[PATCH xf86-video-nouveau 0/4] Compiler warnings series
A short series of compiler visibility warning fixes that I prepared whilst
trialing improvements to xf86-video-nouveau's use of the core xorg-server
utility macros.
Rhys Kidd (4):
wfb: Remove declaration for undefined function nouveau_wfb_init()
dri2: Mark local create/destroy buffer and copy region functions as
static
xv: Mark local NVSetupTexturedVideo function as static
2016 Oct 16
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...44
--- a/src/nvc0_xv.c
+++ b/src/nvc0_xv.c
@@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
{ dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
};
struct nouveau_pushbuf *push = pNv->pushbuf;
- uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode << 18);
float X1, X2, Y1, Y2;
BoxPtr pbox;
int nbox;
@@ -105,71 +104,49 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
PUSH_DATAu(push, pNv->scratch, TIC_OFFSET, 16);
if (id == FOURCC_YV12 || id == FOURCC_I420) {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
+ PUSH_TIC(push, src, packed_y, width, height, 0,
+...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...44
--- a/src/nvc0_xv.c
+++ b/src/nvc0_xv.c
@@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
{ dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
};
struct nouveau_pushbuf *push = pNv->pushbuf;
- uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode << 18);
float X1, X2, Y1, Y2;
BoxPtr pbox;
int nbox;
@@ -105,71 +104,49 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
PUSH_DATAu(push, pNv->scratch, TIC_OFFSET, 16);
if (id == FOURCC_YV12 || id == FOURCC_I420) {
- PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
+ PUSH_TIC(push, src, packed_y, width, height, 0,
+...
2016 Oct 17
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...>> { dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
>> };
>> struct nouveau_pushbuf *push = pNv->pushbuf;
>> - uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode << 18);
>> float X1, X2, Y1, Y2;
>> BoxPtr pbox;
>> int nbox;
>> @@ -105,71 +104,49 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
>>
>> PUSH_DATAu(push, pNv->scratch, TIC_OFFSET, 16);
>> if (id == FOURCC_YV12 || id == FOURCC_I420) {
>> - PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV...
2015 Mar 21
0
[PATCH] use defined method names where available
...push, NV50_3D(TIC_FLUSH), 1);
PUSH_DATA (push, 0);
BEGIN_NV04(push, NV50_3D(BIND_TIC(2)), 1);
diff --git a/src/nv_accel_common.c b/src/nv_accel_common.c
index f0c2d62..9361ce8 100644
--- a/src/nv_accel_common.c
+++ b/src/nv_accel_common.c
@@ -145,13 +145,13 @@ NV11SyncToVBlank(PixmapPtr ppix, BoxPtr box)
head = drmmode_head(crtc);
- BEGIN_NV04(push, SUBC_BLIT(0x0000012C), 1);
+ BEGIN_NV04(push, NV15_BLIT(FLIP_INCR_WRITE), 1);
PUSH_DATA (push, 0);
- BEGIN_NV04(push, SUBC_BLIT(0x00000134), 1);
+ BEGIN_NV04(push, NV15_BLIT(FLIP_CRTC_INCR_READ), 1);
PUSH_DATA (push, head);
BEGIN_NV04(p...
2017 Apr 18
3
[PATCH xserver] Make PixmapDirtyUpdateRec::src a DrawablePtr
...RegionPtr dirty_region)
{
- ScreenPtr pScreen = dirty->src->drawable.pScreen;
- DrawablePtr src = pScreen->root ? &pScreen->root->drawable : &dirty->src->drawable;
+ DrawablePtr src = dirty->src;
+ ScreenPtr pScreen = src->pScreen;
int n;
BoxPtr b;
GCPtr pGC;
@@ -309,7 +307,7 @@ PixmapDirtyCompositeRotate(PixmapPtr dst_pixmap,
PixmapDirtyUpdatePtr dirty,
RegionPtr dirty_region)
{
- ScreenPtr pScreen = dirty->src->drawable.pScreen;
+ ScreenPtr pScreen = dirty->src-...
2016 Oct 27
2
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...c0_xv.c
> @@ -74,7 +74,6 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
> { dst, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR },
> };
> struct nouveau_pushbuf *push = pNv->pushbuf;
> - uint32_t mode = 0xd0005000 | (src->config.nvc0.tile_mode << 18);
> float X1, X2, Y1, Y2;
> BoxPtr pbox;
> int nbox;
> @@ -105,71 +104,49 @@ nvc0_xv_image_put(ScrnInfoPtr pScrn,
>
> PUSH_DATAu(push, pNv->scratch, TIC_OFFSET, 16);
> if (id == FOURCC_YV12 || id == FOURCC_I420) {
> - PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
> + PUSH_TIC(push, s...
2009 Mar 20
12
[Bug 20780] New: nouveau corrupts and crashes on 7800gt when NoAccel= false after a few drawing operations
http://bugs.freedesktop.org/show_bug.cgi?id=20780
Summary: nouveau corrupts and crashes on 7800gt when
NoAccel=false after a few drawing operations
Product: xorg
Version: unspecified
Platform: x86-64 (AMD64)
OS/Version: Linux (All)
Status: NEW
Severity: normal
Priority: medium
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
These are copied directly from the mesa repository.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++
src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++----------------
2 files changed, 892 insertions(+), 340 deletions(-)
create mode 100644 src/hwdefs/gm107_texture.xml.h
diff --git
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
I believe I've addressed all the feedback from the first time around, and
also made fixes necessary for GM20x based on testing results. I believe
now it should actually work for all GM10x and GM20x. Further, GP10x should
be very easy to add, but without someone to actually test I didn't want to
claim support for it.
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update