Displaying 9 results from an estimated 9 matches for "borkag".
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borkage
2015 Apr 29
4
[PATCH v16 13/14] pvqspinlock: Improve slowpath performance by avoiding cmpxchg
...before
> it can enter the halt state. This should give enough time for the
> setting of the locked flag in struct mcs_spinlock to propagate to
> that CPU without using atomic op.
Yuck! I'm not at all sure you can make assumptions like that. And the
worst part is, if it goes wrong the borkage is subtle and painful.
2015 Apr 29
4
[PATCH v16 13/14] pvqspinlock: Improve slowpath performance by avoiding cmpxchg
...before
> it can enter the halt state. This should give enough time for the
> setting of the locked flag in struct mcs_spinlock to propagate to
> that CPU without using atomic op.
Yuck! I'm not at all sure you can make assumptions like that. And the
worst part is, if it goes wrong the borkage is subtle and painful.
2015 May 04
1
[PATCH v16 13/14] pvqspinlock: Improve slowpath performance by avoiding cmpxchg
...t state. This should give enough time for the
> >>setting of the locked flag in struct mcs_spinlock to propagate to
> >>that CPU without using atomic op.
> >Yuck! I'm not at all sure you can make assumptions like that. And the
> >worst part is, if it goes wrong the borkage is subtle and painful.
>
> I do think the code is OK. However, you are right that if my reasoning is
> incorrect, the resulting bug will be really subtle.
So I do not think its correct, imagine the fabrics used for the 4096 cpu
SGI machine, now add some serious traffic to them. There i...
2015 May 04
1
[PATCH v16 13/14] pvqspinlock: Improve slowpath performance by avoiding cmpxchg
...t state. This should give enough time for the
> >>setting of the locked flag in struct mcs_spinlock to propagate to
> >>that CPU without using atomic op.
> >Yuck! I'm not at all sure you can make assumptions like that. And the
> >worst part is, if it goes wrong the borkage is subtle and painful.
>
> I do think the code is OK. However, you are right that if my reasoning is
> incorrect, the resulting bug will be really subtle.
So I do not think its correct, imagine the fabrics used for the 4096 cpu
SGI machine, now add some serious traffic to them. There i...
2015 Apr 29
0
[PATCH v16 13/14] pvqspinlock: Improve slowpath performance by avoiding cmpxchg
...ter the halt state. This should give enough time for the
>> setting of the locked flag in struct mcs_spinlock to propagate to
>> that CPU without using atomic op.
>
> Yuck! I'm not at all sure you can make assumptions like that. And the
> worst part is, if it goes wrong the borkage is subtle and painful.\
I have to agree with Peter.
But it goes beyond this particular patch. Patterns like this:
xchg(&pn->mayhalt, true);
are just evil and disgusting. Even befoe this patch, that code had
(void)xchg(&pn->state, vcpu_halted);
which is *w...
2015 Apr 30
0
[PATCH v16 13/14] pvqspinlock: Improve slowpath performance by avoiding cmpxchg
...an enter the halt state. This should give enough time for the
>> setting of the locked flag in struct mcs_spinlock to propagate to
>> that CPU without using atomic op.
> Yuck! I'm not at all sure you can make assumptions like that. And the
> worst part is, if it goes wrong the borkage is subtle and painful.
I do think the code is OK. However, you are right that if my reasoning
is incorrect, the resulting bug will be really subtle. So I am going to
withdraw this particular patch as it has no functional impact to the
overall patch series. Please let me know if you have any ot...
2010 Jun 17
2
MEMDISK, MDISKCHK.COM
Just a slight poke regarding the MEMDISK and MDISKCHK.COM possibilities
available here[1]. Review by non-hpas is welcome, too. Thanks! - Shao
[1]
http://git.zytor.com/?p=users/sha0/syslinux.git;a=shortlog;h=refs/heads/
mdiskchk_enh2
2015 Apr 24
16
[PATCH v16 00/14] qspinlock: a 4-byte queue spinlock with PV support
v15->v16:
- Remove the lfsr patch and use linear probing as lfsr is not really
necessary in most cases.
- Move the paravirt PV_CALLEE_SAVE_REGS_THUNK code to an asm header.
- Add a patch to collect PV qspinlock statistics which also
supersedes the PV lock hash debug patch.
- Add PV qspinlock performance numbers.
v14->v15:
- Incorporate PeterZ's v15 qspinlock patch and improve
2015 Apr 24
16
[PATCH v16 00/14] qspinlock: a 4-byte queue spinlock with PV support
v15->v16:
- Remove the lfsr patch and use linear probing as lfsr is not really
necessary in most cases.
- Move the paravirt PV_CALLEE_SAVE_REGS_THUNK code to an asm header.
- Add a patch to collect PV qspinlock statistics which also
supersedes the PV lock hash debug patch.
- Add PV qspinlock performance numbers.
v14->v15:
- Incorporate PeterZ's v15 qspinlock patch and improve