search for: boot_pf_handler

Displaying 8 results from an estimated 8 matches for "boot_pf_handler".

[PATCH 14/70] x86/boot/compressed/64: Add page-fault handler
2020 Apr 02
0
[PATCH 14/70] x86/boot/compressed/64: Add page-fault handler
.../idt_64.c > index 46ecea671b90..84ba57d9d436 100644 > --- a/arch/x86/boot/compressed/idt_64.c > +++ b/arch/x86/boot/compressed/idt_64.c > @@ -39,5 +39,7 @@ void load_stage2_idt(void) > { > boot_idt_desc.address = (unsigned long)boot_idt; > > + set_idt_entry(X86_TRAP_PF, boot_pf_handler); > + > load_boot_idt(&boot_idt_desc); > } > diff --git a/arch/x86/boot/compressed/idt_handlers_64.S b/arch/x86/boot/compressed/idt_handlers_64.S > index 3d86ab35ef52..bfb3fc5aa144 100644 > --- a/arch/x86/boot/compressed/idt_handlers_64.S > +++ b/arch/x86/boot/compressed...
[PATCH 18/62] x86/boot/compressed/64: Setup GHCB Based VC Exception handler
2020 Feb 11
0
[PATCH 18/62] x86/boot/compressed/64: Setup GHCB Based VC Exception handler
...pports Secure Memory diff --git a/arch/x86/boot/compressed/idt_64.c b/arch/x86/boot/compressed/idt_64.c index bdd20dfd1fd0..eebb2f857dac 100644 --- a/arch/x86/boot/compressed/idt_64.c +++ b/arch/x86/boot/compressed/idt_64.c @@ -45,5 +45,9 @@ void load_stage2_idt(void) set_idt_entry(X86_TRAP_PF, boot_pf_handler); +#ifdef CONFIG_AMD_MEM_ENCRYPT + set_idt_entry(X86_TRAP_VC, boot_stage2_vc_handler); +#endif + load_boot_idt(&boot_idt_desc); } diff --git a/arch/x86/boot/compressed/idt_handlers_64.S b/arch/x86/boot/compressed/idt_handlers_64.S index 330eb4e5c8b3..3c71a11beee0 100644 --- a/arch/x86/boot...
[PATCH 14/62] x86/boot/compressed/64: Add stage1 #VC handler
2020 Feb 11
0
[PATCH 14/62] x86/boot/compressed/64: Add stage1 #VC handler
...it a/arch/x86/boot/compressed/idt_handlers_64.S b/arch/x86/boot/compressed/idt_handlers_64.S index f7f1ea66dcbf..330eb4e5c8b3 100644 --- a/arch/x86/boot/compressed/idt_handlers_64.S +++ b/arch/x86/boot/compressed/idt_handlers_64.S @@ -71,3 +71,7 @@ SYM_FUNC_END(\name) .code64 EXCEPTION_HANDLER boot_pf_handler do_boot_page_fault error_code=1 + +#ifdef CONFIG_AMD_MEM_ENCRYPT +EXCEPTION_HANDLER boot_stage1_vc_handler no_ghcb_vc_handler error_code=1 +#endif diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h index 4e5bc688f467..0e3508c5c15c 100644 --- a/arch/x86/boot/compressed/mi...
[PATCH 14/62] x86/boot/compressed/64: Add stage1 #VC handler
2020 Feb 11
2
[PATCH 14/62] x86/boot/compressed/64: Add stage1 #VC handler
...4.S b/arch/x86/boot/compressed/idt_handlers_64.S > index f7f1ea66dcbf..330eb4e5c8b3 100644 > --- a/arch/x86/boot/compressed/idt_handlers_64.S > +++ b/arch/x86/boot/compressed/idt_handlers_64.S > @@ -71,3 +71,7 @@ SYM_FUNC_END(\name) > .code64 > > EXCEPTION_HANDLER boot_pf_handler do_boot_page_fault error_code=1 > + > +#ifdef CONFIG_AMD_MEM_ENCRYPT > +EXCEPTION_HANDLER boot_stage1_vc_handler no_ghcb_vc_handler error_code=1 > +#endif > diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h > index 4e5bc688f467..0e3508c5c15c 10064...
[PATCH 14/62] x86/boot/compressed/64: Add stage1 #VC handler
2020 Feb 11
2
[PATCH 14/62] x86/boot/compressed/64: Add stage1 #VC handler
...4.S b/arch/x86/boot/compressed/idt_handlers_64.S > index f7f1ea66dcbf..330eb4e5c8b3 100644 > --- a/arch/x86/boot/compressed/idt_handlers_64.S > +++ b/arch/x86/boot/compressed/idt_handlers_64.S > @@ -71,3 +71,7 @@ SYM_FUNC_END(\name) > .code64 > > EXCEPTION_HANDLER boot_pf_handler do_boot_page_fault error_code=1 > + > +#ifdef CONFIG_AMD_MEM_ENCRYPT > +EXCEPTION_HANDLER boot_stage1_vc_handler no_ghcb_vc_handler error_code=1 > +#endif > diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h > index 4e5bc688f467..0e3508c5c15c 10064...
[PATCH 18/70] x86/boot/compressed/64: Add stage1 #VC handler
2020 Apr 06
0
[PATCH 18/70] x86/boot/compressed/64: Add stage1 #VC handler
...andlers_64.S b/arch/x86/boot/compressed/idt_handlers_64.S > index bfb3fc5aa144..67ddafab2943 100644 > --- a/arch/x86/boot/compressed/idt_handlers_64.S > +++ b/arch/x86/boot/compressed/idt_handlers_64.S > @@ -75,3 +75,7 @@ SYM_FUNC_END(\name) > .code64 > > EXCEPTION_HANDLER boot_pf_handler do_boot_page_fault error_code=1 > + > +#ifdef CONFIG_AMD_MEM_ENCRYPT > +EXCEPTION_HANDLER boot_stage1_vc_handler vc_no_ghcb_handler error_code=1 Like the others boot_stage1_vc do_boot_stage1_vc ... -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette
[RFC PATCH 00/62] Linux as SEV-ES Guest Support
2020 Feb 11
83
[RFC PATCH 00/62] Linux as SEV-ES Guest Support
Hi, here is the first public post of the patch-set to enable Linux to run under SEV-ES enabled hypervisors. The code is mostly feature-complete, but there are still a couple of bugs to fix. Nevertheless, given the size of the patch-set, I think it is about time to ask for initial feedback of the changes that come with it. To better understand the code here is a quick explanation of SEV-ES first.
[RFC PATCH 00/62] Linux as SEV-ES Guest Support
2020 Feb 11
83
[RFC PATCH 00/62] Linux as SEV-ES Guest Support
Hi, here is the first public post of the patch-set to enable Linux to run under SEV-ES enabled hypervisors. The code is mostly feature-complete, but there are still a couple of bugs to fix. Nevertheless, given the size of the patch-set, I think it is about time to ask for initial feedback of the changes that come with it. To better understand the code here is a quick explanation of SEV-ES first.