search for: boot_falcon

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot:

...v/secboot/acr_r352.c index a7213542..00095ef8 100644 --- a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -924,6 +924,19 @@ acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb) } } + /* reset the PMU if needed */ + if (acr->base.boot_falcon == NVKM_SECBOOT_FALCON_PMU && + !nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_PMU)) { + struct nvkm_pmu *pmu = subdev->device->pmu; + if (pmu) { + ret = nvkm_subdev_init(&pmu->subdev); + if (ret < 0) { + nvkm_error(subdev, "Failed to reset PMU\n");...

Hi Alexandre, On 18 January 2016 at 06:10, Alexandre Courbot <acourbot at nvidia.com> wrote: [snip] > +static const char * > +managed_falcons_names[] = { > + [NVKM_SECBOOT_FALCON_PMU] = "PMU", > + [NVKM_SECBOOT_FALCON_RESERVED] = "<invalid>", "<reserved>" perhaps ? we already have one invalid below. > + [NVKM_SECBOOT_FALCON_FECS] = "FECS", > + [NVKM_SECBOOT_FALCON_GPCCS] = "GPCCS", &gt...

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

...t acr_r352_ls_func *func = - acr->func->ls_func[img->falcon_id]; + acr->func->ls_func[_img->falcon_id]; /* Fill WPR header */ - whdr->falcon_id = img->falcon_id; + whdr->falcon_id = _img->falcon_id; whdr->bootstrap_owner = acr->base.func->boot_falcon; whdr->status = LSF_IMAGE_STATUS_COPY; /* Align, save off, and include an LSB header size */ offset = ALIGN(offset, LSF_LSB_HEADER_ALIGN); whdr->lsb_offset = offset; - offset += sizeof(struct lsf_lsb_header); + offset += sizeof(*lhdr); /* * Align, save off, and include the or...

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

On 01/21/2016 10:09 PM, Emil Velikov wrote: > Hi Alexandre, > > On 18 January 2016 at 06:10, Alexandre Courbot <acourbot at nvidia.com> wrote: > > [snip] >> +static const char * >> +managed_falcons_names[] = { >> + [NVKM_SECBOOT_FALCON_PMU] = "PMU", >> + [NVKM_SECBOOT_FALCON_RESERVED] = "<invalid>", > "<reserved>" perhaps ? we already have one invalid below. Does <reserved> really mean: "we don't want to tell you?" here? :) > >> + [NVKM_...

...95ef8 100644 > --- a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c > +++ b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c > @@ -924,6 +924,19 @@ acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb) > } > } > > + /* reset the PMU if needed */ > + if (acr->base.boot_falcon == NVKM_SECBOOT_FALCON_PMU && > + !nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_PMU)) { > + struct nvkm_pmu *pmu = subdev->device->pmu; > + if (pmu) { > + ret = nvkm_subdev_init(&pmu->subdev); > + if (ret < 0) { > + nvkm_error(subdev, "...

...ivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c index 9424803b9ef4..dfc0d50f080b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c @@ -226,7 +226,7 @@ acr_boot_falcon(struct nvkm_msgqueue *priv, enum nvkm_secboot_falcon falcon) return 0; } -const struct nvkm_msgqueue_acr_func +static const struct nvkm_msgqueue_acr_func msgqueue_0148cdec_acr_func = { .boot_falcon = acr_boot_falcon, }; @@ -237,7 +237,7 @@ msgqueue_0148cdec_dtor(struct nvkm_msgqueue *queue...

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

...nc[img->falcon_id]; - if (img->ucode_header) { - nvkm_fatal(acr->base.subdev, - "images withough loader are not supported yet!\n"); - return offset; - } - /* Fill WPR header */ whdr->falcon_id = img->falcon_id; whdr->bootstrap_owner = acr->base.func->boot_falcon; @@ -309,7 +303,6 @@ ls_ucode_mgr_cleanup(struct ls_ucode_mgr *mgr) list_for_each_entry_safe(img, t, &mgr->img_list, node) { kfree(img->ucode_data); - kfree(img->ucode_header); kfree(img); } } @@ -362,6 +355,10 @@ ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct ls_uco...

...+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKM_SECURE_BOOT_H__ +#define __NVKM_SECURE_BOOT_H__ + +#include <core/subdev.h> + +enum nvkm_secboot_falcon { + NVKM_SECBOOT_FALCON_PMU = 0, + NVKM_SECBOOT_FALCON_RESERVED = 1, + NVKM_SECBOOT_FALCON_FECS = 2, + NVKM_SECBOOT_FALCON_GPCCS = 3, + NVKM_SECBOOT_FALCON_END = 4, + NVKM_SECBOOT_FALCON_INVALID = 0xffffffff, +}; + +/** + * @falcon_id: falcon that will perform secure boot + * @base: base IO addre...

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

...ouveau/include/nvkm/subdev/secboot.h b/drm/nouveau/include/nvkm/subdev/secboot.h index f40b57567676..a509f2b4aa5f 100644 --- a/drm/nouveau/include/nvkm/subdev/secboot.h +++ b/drm/nouveau/include/nvkm/subdev/secboot.h @@ -53,4 +53,6 @@ bool nvkm_secboot_is_managed(struct nvkm_secboot *, enum nvkm_secboot_falcon); int nvkm_secboot_reset(struct nvkm_secboot *, u32 falcon); int nvkm_secboot_start(struct nvkm_secboot *, u32 falcon); +int gm200_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **); + #endif diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c...

...goto done; + goto end; /* Load the HS bootloader into the falcon's IMEM/DMEM */ gm200_secboot_load_hs_bl(gsb, &bl_desc, bl_desc_size); @@ -1122,17 +1122,9 @@ gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob, /* Start the HS bootloader */ ret = nvkm_secboot_falcon_run(&gsb->base); if (ret) - goto done; - -done: - /* Restore the original DMA addresses */ - vma_addr = flcn64_to_u64(desc->code_dma_base) - vma.offset; - desc->code_dma_base.lo = lower_32_bits(vma_addr); - desc->code_dma_base.hi = upper_32_bits(vma_addr); - vma_addr = flcn64_to_...