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...et CPURegs:$dst, > (add (MipsHi tglobaladdr:$addr0), (MipsLo > tglobaladdr:$addr1)))], IIAlu>; > > Note that you still need to find a way to print "g1" instead of "%hi(g1)". > > On Wed, Oct 5, 2011 at 4:01 PM, Gang-Ryung Uh <guh at boisestate.edu> wrote: > > Hi, > > In order to emit "la $4,ADDR" instead of lui followed by addiu to > load > > the data address, could you advise what is proper way to revise td files > in > > the MIPS target? > > Thanks, > > > > -- > >...

...(add (MipsHi tglobaladdr:$addr0), (MipsLo > > tglobaladdr:$addr1)))], IIAlu>; > > > > Note that you still need to find a way to print "g1" instead of > "%hi(g1)". > > > > On Wed, Oct 5, 2011 at 4:01 PM, Gang-Ryung Uh <guh at boisestate.edu> > wrote: > > > Hi, > > > In order to emit "la $4,ADDR" instead of lui followed by addiu to > load > > > the data address, could you advise what is proper way to revise td > files in > > > the MIPS target? > > > Thanks, &gt...

...CPURegs:$dst, > (add (MipsHi tglobaladdr:$addr0), (MipsLo > tglobaladdr:$addr1)))], IIAlu>; > > Note that you still need to find a way to print "g1" instead of "%hi(g1)". > > On Wed, Oct 5, 2011 at 4:01 PM, Gang-Ryung Uh <guh at boisestate.edu> wrote: > > Hi, > > In order to emit "la $4,ADDR" instead of lui followed by addiu to load > > the data address, could you advise what is proper way to revise td files in > > the MIPS target? > > Thanks, > > > > -- > > Gang-Ryung...

...t; instead of lui followed by addiu to load the data address, could you advise what is proper way to revise td files in the MIPS target? Thanks, -- Gang-Ryung Uh, Associate Professor Department of Computer Science College of Engineering, Boise State Univerisity tel: 1 208 426-5691 e-mail:guh at boisestate.edu http://cs.boisestate.edu/~uh -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111005/623e2d60/attachment.html>

...;la $dst, $addr0", [(set CPURegs:$dst, (add (MipsHi tglobaladdr:$addr0), (MipsLo tglobaladdr:$addr1)))], IIAlu>; Note that you still need to find a way to print "g1" instead of "%hi(g1)". On Wed, Oct 5, 2011 at 4:01 PM, Gang-Ryung Uh <guh at boisestate.edu> wrote: > Hi, >      In order to emit "la $4,ADDR" instead of lui followed by addiu to load > the data address, could you advise what is proper way to revise td files in > the MIPS target? > Thanks, > > -- > Gang-Ryung Uh, Associate Professor > Department...

...load the data address, could you advise what is proper way to revise td > files in the MIPS target? > > Why? > > -eric > > -- Gang-Ryung Uh, Associate Professor Department of Computer Science College of Engineering, Boise State Univerisity tel: 1 208 426-5691 e-mail:guh at boisestate.edu http://cs.boisestate.edu/~uh -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111005/3e386d99/attachment.html>

Hi, I wonder what PRE algorithm is used for the GVN.cpp in LLVM. Any reference will be appreciated. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140930/3d7f74e3/attachment.html>

...t; > If you do not specify the target cpu with -mcpu, by default it will > generate code for Mips1, which has not been tested as thoroughly as Mips32r2 > (-mcpu=4ke) or Mips2 (-mcpu=mips2). > > The default ABI is o32. > > On Sat, Jul 9, 2011 at 8:32 AM, Gang-Ryung Uh <guh at boisestate.edu> wrote: > >> We are trying to use LLVM (Clang as the C frontend) to generate code for >> 32-bit MIPS (little-endian)l, which can run on simplescalar 3.0 >> sslittle-na-sstrix platform. Can you advise what would be the right way to >> use the LLVM compiler infrastru...

...s (the -march option is redundant) If you do not specify the target cpu with -mcpu, by default it will generate code for Mips1, which has not been tested as thoroughly as Mips32r2 (-mcpu=4ke) or Mips2 (-mcpu=mips2). The default ABI is o32. On Sat, Jul 9, 2011 at 8:32 AM, Gang-Ryung Uh <guh at boisestate.edu> wrote: > We are trying to use LLVM (Clang as the C frontend) to generate code for > 32-bit MIPS (little-endian)l, which can run on simplescalar 3.0 > sslittle-na-sstrix platform. Can you advise what would be the right way to > use the LLVM compiler infrastructure? > > The...

We are trying to use LLVM (Clang as the C frontend) to generate code for 32-bit MIPS (little-endian)l, which can run on simplescalar 3.0 sslittle-na-sstrix platform. Can you advise what would be the right way to use the LLVM compiler infrastructure? The following is the one I used, but it appears that it produce the code in big-endian (and I wonder whether the calling convention is right.) To

On Jul 15, 2011, at 10:13 AM, Gang-Ryung Uh wrote: > Hi, > > We have tried and generate assembly code for very simple test C code. But, binutils-2.5.2 (simplesim-3.0) cannot handle the produced assembly code with the following complaints. Could you advise which version of bitutils that we need to use for mips code with LLVM with Clang? Thanks, Something released in the last 10

...omething released in the last 10 years maybe? Just download something > recent from gnu.org and you should be fine. > > -eric > > -- Gang-Ryung Uh, Associate Professor Department of Computer Science College of Engineering, Boise State Univerisity tel: 1 208 426-5691 e-mail:guh at boisestate.edu http://cs.boisestate.edu/~uh -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110715/bc464234/attachment.html>

...erate mips code for binutils-1.5. Having said this, could you advise which module(s) in LLVM we need to modify? Thanks in advance. Regards, -- -- Gang-Ryung Uh, Associate Professor Department of Computer Science College of Engineering, Boise State Univerisity tel: 1 208 426-5691 e-mail:guh at boisestate.edu http://cs.boisestate.edu/~uh -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110717/fecd4f5d/attachment.html>

On Oct 5, 2011, at 4:01 PM, Gang-Ryung Uh wrote: > Hi, > > In order to emit "la $4,ADDR" instead of lui followed by addiu to load the data address, could you advise what is proper way to revise td files in the MIPS target? Why? -eric

...vel language semantics, LLVM IR may not be right for you, as most of that information is lost by the time the code has been converted to LLVM IR. -Dave ------------------------------ Message: 2 Date: Wed, 5 Oct 2011 17:01:48 -0600 From: Gang-Ryung Uh <guh at boisestate.edu> Subject: [LLVMdev] MIPS 32bit code generation To: llvmdev <llvmdev at cs.uiuc.edu> Message-ID: <CAMp0i=AMYGY6OpepCKdbk6NMzaMZum6dtXRPN9F3ow=vL4P-MA at mail.gmail.com> Content-Type: text/plain; charset="iso-8859-1" Hi, In order to emit "la $4,ADDR&qu...

Hi, Target architecture for llc can be specified using -march, -mcpu, -mattr options. Is it possible to override target CPU attributes when using llvm-gcc compiler? Regards, Sergey Y.

Is it possible to configure llc to generate code for other architectures? For instance, what I need to do to generate Sparc machine code? Thanks. --Gang -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100316/253bd016/attachment.html>

*What would be the recommended way to debug LLVM opt pass? Is there any way to perform source level debugging on a particular opt pass? * *-- UGR* -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100110/e250208a/attachment.html>

I am using LLVM 2.6 and I have a question on the use of the BasicBlock::iterator to hoist loop invariant instructions to the loop preheader. When I process the instructions backward as shown in the following code, I got the following error right after the "hoist(I)" is done. Can anyone advise whether I am misusing BasicBlock::iterator? /opt/llvms/src/llvm_26/

I wonder whether this question is appropriate to this forum or not; if not, please educate me. For the following command line arguments, what happens to the optimization phases when the licm phase moves out loop invariant instructions to loop preheaders? opt -simplifycfg -instcombine -inline -globaldce -instcombine -simplifycfg -scalarrepl -mem2reg -verify -sccp -adce -licm -instcombine -dce