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Hi! Am 05.11.2014 um 16:05 schrieb Tim Northover <t.p.northover at gmail.com>: > Hi Boris, > > On 5 November 2014 06:47, Boris Boesler <baembel at gmx.de> wrote: >> Cross-check: Move the MV-patterns from the beginning to the end. Voila, it works. > > It would be better to delete those patterns entirely. They'll always > match (if asked) and never give a sane result. Hm, these are no patterns like "...

...*N), approximately 11 nodes are missing. The first add-node (v1+v2) is missing. Is it normal that not all nodes are passes to ::Select()? Thanks, Boris Am 30.10.2014 um 19:23 schrieb Quentin Colombet <qcolombet at apple.com>: > Hi Boris, > > On Oct 29, 2014, at 10:35 AM, Boris Boesler <baembel at gmx.de> wrote: > >> Hi Quentin, >> >> yes, this happens quite late. With the Option --debug-pass=Structure it's in or after "Assembly Printer". >> I do have a very simple DAGToDAGISel::Select() method: >> >> SDNode *MyTargetD...

Hi Quentin, Am 01.11.2014 um 00:39 schrieb Quentin Colombet <qcolombet at apple.com>: > > On Oct 31, 2014, at 11:00 AM, Boris Boesler <baembel at gmx.de> wrote: > >> Hi Quentin, >> >> I added some debug output (N->dump()) in ::Select(SDNode*N) and compared it to the dot/Graphviz output (-view-legalize-types-dags; the last one with correct code). I found out, that some SDNodes are not passed to the...

On Thu, Jun 20, 2013 at 6:14 AM, Boris Boesler <baembel at gmx.de> wrote: > Hi! > > I want to write a LLVM back-end for a bit addressing target architecture. > > http://llvm.org/docs/GetElementPtr.html#i-m-writing-a-backend-for-a-target-which-needs-custom-lowering-for-gep-how-do-i-do-thisstates quite clearly that some add...

Hi Quentin, Am 03.11.2014 um 23:30 schrieb Quentin Colombet <qcolombet at apple.com>: >> Continuing at 4309 >> Match failed at index 4310 >> Continuing at 4322 >> Morphed node: 0x7fef2a033610: i32 = MVrr 0x7fef2a033610 [ORD=21] >> >> >> Does the add operation become a MOVE instruction, or is this a chain of rules? > > Yes, your add becomes

Hi! I want to write a LLVM back-end for a bit addressing target architecture. http://llvm.org/docs/GetElementPtr.html#i-m-writing-a-backend-for-a-target-which-needs-custom-lowering-for-gep-how-do-i-do-this states quite clearly that some additional work must be done for this sort of architecture. Is this still true? Is there a project/branch to make it more flexible? Support for any memory

...late in the pipeline of the backend (i.e., after SSA form has been deconstructed). > Do you have any custom pass between instruction selection and the PHIElimination pass? > > If so, I would look into them. > > Cheers, > -Quentin > >> On Oct 24, 2014, at 7:53 AM, Boris Boesler <baembel at gmx.de> wrote: >> >> Hi! >> >> During my backend development I get the error message for some tests: >> *** Bad machine code: Virtual register def doesn't dominate all uses. *** >> >> (C source-code, byte-code disassembly and printe...

...:56 schrieb Eli Friedman <efriedma at quicinc.com>: > > Hmm. Then I'm not sure; at first glance, the debug output looks fine either way. Could you show the IR after LSR, and explain why it's wrong? > > -Eli > >> -----Original Message----- >> From: Boris Boesler <baembel at gmx.de> >> Sent: Tuesday, June 9, 2020 11:59 AM >> To: Eli Friedman <efriedma at quicinc.com> >> Cc: llvm-dev at lists.llvm.org >> Subject: [EXT] Re: [llvm-dev] LoopStrengthReduction generates false code >> >> Hm, no. I expect byte addres...

Hi! I'm making a strange observation in my backend, that ends in illegal code: Version 1: - I lower FrameIndex to TargetFrameIndex (nothing special) - I generate a special address-register ADD instruction in eliminateFrameIndex() to write FramePointer + offset into a new address-register - I use explicit load and store and address-registers in my target instruction patterns: eg (store

...uot;memory is not byte addressed", but you never fixed ScalarEvolution to handle that, so it's modeling the GEP in a way you're not expecting. > > -Eli > >> -----Original Message----- >> From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Boris Boesler >> via llvm-dev >> Sent: Tuesday, June 9, 2020 1:17 AM >> To: llvm-dev at lists.llvm.org >> Subject: [EXT] [llvm-dev] LoopStrengthReduction generates false code >> >> Hi. >> >> In my backend I get false code after using StrengthLoopReduction. In the...

Hi! I started writing a LLVM backend for a custom architecture. I have some register and instruction .td files and some other files/classes like a MCStreamer for assembler output. At the moment I can compile some empty programs so far. I implemented the method ::eliminateFrameIndex() similar to the Sparc and ARM backend. The method looks like this: // frame pointer is in reg of class

I'm targeting a machine that can only load and store aligned 64-bit words, but I'd like to be able to pack 8-, 16-, and 32-bit values into these words. Loads will require various shifts and masks; stores are more complicated. Does LLVM provide any support for such things? Is there an example target I can look at for ideas? Thanks, Preston -------------- next part -------------- An HTML

Hi! During my backend development I get the error message for some tests: *** Bad machine code: Virtual register def doesn't dominate all uses. *** (C source-code, byte-code disassembly and printed machine code at the end of the email) The first USE of vreg4 in BB#1 has no previous DEF in BB#0 or #1. But why? I can't see how the LLVM byte-code is transformed to the lower machine code.

Hi! >> I'm writing a new back-end for a new architecture. First, I'll do >> some "tests" with an existing back-end (I chose the Sparc back-end). >> My architecture has special address-registers and I want to add such >> new address-registers to my Sparc back-end. >> .... >> The GlobalAddress for variable c is replaced by an ADD(HI(c), LO

On Oct 19, 2007, at 8:15 AM, Boris Boesler wrote: > Hi! > > I'm writing a new back-end for a new architecture. First, I'll do > some "tests" with an existing back-end (I chose the Sparc back-end). > My architecture has special address-registers and I want to add such > new address-registers to my Sparc...

Hi! I'm writing a new back-end for a new architecture. First, I'll do some "tests" with an existing back-end (I chose the Sparc back-end). My architecture has special address-registers and I want to add such new address-registers to my Sparc back-end. 1) I defined a new register call AddrRegs 2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. )) 3) I

Hi Quentin, >> Yes, the dags in view-isel-dags and view-legalize-types-dags are correct (the add operations are here and are their results are used) and the dags are the same. > > And what about view-sched-dags? The DAG looks like I described below (*) > This one should give you what has been selected. So if this is not correct, you have indeed a problem in the selection

Hi. In my backend I get false code after using StrengthLoopReduction. In the generated code the loop index variable is multiplied by 8 (correct, everything is 64 bit aligned) to get an address offset, and the index variable is incremented by 1*8, which is not correct. It should be incremented by 1 only. The factor 8 appears again. I compared the debug output

Hi! I have some problems with spill/reload and register scavenging which result in illegal code. As our apps, compiled by LLVM and our backend, become more and more complex we have the following problem with our backend: In most cases registers are spilled on function entry to stack slots and reloaded on function exit. At some points registers are spilled and reloaded via register scavenging.

Hi! This questions seems a little bit stupid, but I'll ask anyway ;-) How do I configure llvm-gcc (version 4.0.1) without having a gcc back-end, but a LLVM back-end for my new architecture? Thanks in advance, Boris