Displaying 11 results from an estimated 11 matches for "body10".
2015 Sep 20
2
simplifycfg not happening?
...x double>* %14, align 8, !dbg !20
%15 = bitcast double* %10 to <2 x double>*, !dbg !20
store <2 x double> %13, <2 x double>* %15, align 8, !dbg !20
%index.next.1 = add nsw i64 %index, 8, !dbg !18
%16 = icmp eq i64 %index.next.1, 1000, !dbg !18
br i1 %16, label %vector.body10.preheader, label %vector.body, !dbg !18,
!llvm.loop !21
vector.body10.preheader: ; preds = %vector.body
br label %vector.body10, !dbg !24
vector.body10: ; preds = %vector.body10,
%vector.body10.preheader
%index13 = phi i64 [ 0, %vect...
2017 Jan 24
3
[InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
On Tue, Jan 24, 2017 at 1:20 PM, Sanjay Patel via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
>
> I started looking at the log files that you attached, and I'm confused.
> The code that is supposedly causing the perf regression is created by the
> loop vectorizer, right? Except the bad code is not in the "vector.body", so
> is there something peculiar about
2020 May 17
2
Question about the order of predecessors in LoopVectorizer with VPlanNatviePath
Hi All,
I have got one domination error after running LoopVectorizer with
VPlanNatviePath.
Let's see simple IR snippet after loop vectorization with VPlanNatviePath.
vector.body:
...
br label %for.body10.preheader67
for.body10.preheader67: ; preds =
%for.cond.cleanup972, %vector.body
%vec.phi = phi <4 x i64> [ zeroinitializer, %for.cond.cleanup972 ],
[ %8, %vector.body ]
...
for.cond.cleanup972: ; preds = %for.body1068
%8 = add nuw nsw &l...
2012 Jan 26
0
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
On Thu, Jan 26, 2012 at 3:41 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> On Thu, 2012-01-26 at 15:36 -0600, Sebastian Pop wrote:
>> arm-none-linux-gnueabi
>
> Indeed, adding -ccc-host-triple arm-none-linux-gnueabi I also get
Minor remark: please use -target instead of -ccc-host-triple that is
now deprecated.
Thanks for looking at this testcase.
Sebastian
--
Qualcomm
2015 Sep 20
2
simplifycfg not happening?
...%15 = bitcast double* %10 to <2 x double>*, !dbg !20
>> store <2 x double> %13, <2 x double>* %15, align 8, !dbg !20
>> %index.next.1 = add nsw i64 %index, 8, !dbg !18
>> %16 = icmp eq i64 %index.next.1, 1000, !dbg !18
>> br i1 %16, label %vector.body10.preheader, label %vector.body, !dbg
>> !18, !llvm.loop !21
>>
>> vector.body10.preheader: ; preds = %vector.body
>> br label %vector.body10, !dbg !24
>>
>> vector.body10: ; preds =
>> %vector.bod...
2012 Jan 26
2
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
On Thu, 2012-01-26 at 15:36 -0600, Sebastian Pop wrote:
> arm-none-linux-gnueabi
Indeed, adding -ccc-host-triple arm-none-linux-gnueabi I also get
vectorization (even though I don't get vectorization when targeting
x86_64). I'll let you know what I find.
-Hal
--
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory
2012 Jan 26
0
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
...pairs
> BBV: done!
> BBV: fusing loop #1 for for.end in main...
> BBV: found 0 instructions with candidate pairs
> BBV: done!
> BBV: fusing loop #1 for for.cond7.preheader in main...
> BBV: found 0 instructions with candidate pairs
> BBV: done!
> BBV: fusing loop #1 for for.body10 in main...
> BBV: found 16 instructions with candidate pairs
> BBV: found 62 pair connections.
> BBV: selected 0 pairs.
> BBV: done!
> BBV: fusing loop #1 for for.inc45 in main...
> BBV: found 0 instructions with candidate pairs
> BBV: done!
> BBV: fusing loop #1 for for.end...
2012 Jan 26
3
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
...BBV: found 0 instructions with candidate pairs
BBV: done!
BBV: fusing loop #1 for for.end in main...
BBV: found 0 instructions with candidate pairs
BBV: done!
BBV: fusing loop #1 for for.cond7.preheader in main...
BBV: found 0 instructions with candidate pairs
BBV: done!
BBV: fusing loop #1 for for.body10 in main...
BBV: found 16 instructions with candidate pairs
BBV: found 62 pair connections.
BBV: selected 0 pairs.
BBV: done!
BBV: fusing loop #1 for for.inc45 in main...
BBV: found 0 instructions with candidate pairs
BBV: done!
BBV: fusing loop #1 for for.end47 in main...
BBV: found 3 instructions...
2012 Jan 26
0
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
On Thu, Jan 26, 2012 at 2:49 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> Thanks! Did you compile with any non-default flags other than -mllvm
> -vectorize?
I used -O3 and -vectorize, no other non-default flags.
Sebastian
--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum
2012 Jan 26
2
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
On Thu, 2012-01-26 at 14:34 -0600, Sebastian Pop wrote:
> On Tue, Jan 24, 2012 at 6:41 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> >> enabling vectorization gets the performance down by 80% on ARM.
> >> I will prepare a reduced testcase and try to find out the reason.
> >> As a first shot, I would say that this comes from the vectorization of
> >> code
2013 Feb 14
1
[LLVMdev] LiveIntervals analysis problem
...elementptr inbounds [13 x i16]* %p.i, i32 0, i32 10
%arrayidx26.8.i = getelementptr inbounds [13 x i16]* %pprod, i32 0, i32 10
%arrayidx26.9.i = getelementptr inbounds [13 x i16]* %pprod, i32 0, i32 11
%arrayidx26.10.i = getelementptr inbounds [13 x i16]* %pprod, i32 0, i32 12
br label %for.body10
for.cond22.preheader: ; preds = %if.end
%3 = load i16* %arraydecay, align 2, !tbaa !5
store i16 %3, i16* %b, align 2, !tbaa !5
%4 = load i16* %arrayidx4, align 2, !tbaa !5
store i16 %4, i16* %arrayidx3, align 2, !tbaa !5
%5 = load i16* %arrayidx5, align 2, !tb...