Displaying 3 results from an estimated 3 matches for "bltz".
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blitz
2012 Apr 25
3
[LLVMdev] Not enough optimisations in the SelectionDAG phase?
...%28 = load volatile i32* inttoptr (i64 2149581832 to i32*), align 8
%29 = icmp slt i32 %28, 0
br i1 %29, label %27, label %loop.exit
loop.exit: ; preds = %27
llc will generate following MIPS code,
$BB0_1:
lui $3, 32800
ori $3, $3, 1032
lw $3, 0($3)
bltz $3, $BB0_1
nop
# BB#2:
The two operation lui and ori which are used to calculate memory address
actually are loop invariants. They supposed to be moved out of the loop. I
thought it might be a limitation of the MIPS backend. Then I tried the ARM
backend,
.LBB1_1:
ldr r2, .LCPI1_2
ldr r...
2012 Apr 29
0
[LLVMdev] Not enough optimisations in the SelectionDAG phase?
...i32 %28, 0
> br i1 %29, label %27, label %loop.exit
>
> loop.exit: ; preds = %27
>
> llc will generate following MIPS code,
>
> $BB0_1:
> lui $3, 32800
> ori $3, $3, 1032
> lw $3, 0($3)
> bltz $3, $BB0_1
> nop
> # BB#2:
>
>
> The two operation lui and ori which are used to calculate memory address actually are loop invariants. They supposed to be moved out of the loop. I thought it might be a limitation of the MIPS backend. Then I tried the ARM backend,
>
>...
2012 Apr 29
1
[LLVMdev] Not enough optimisations in the SelectionDAG phase?
...;> br i1 %29, label %27, label %loop.exit
>>
>> loop.exit: ; preds = %27
>>
>> llc will generate following MIPS code,
>>
>> $BB0_1:
>> lui $3, 32800
>> ori $3, $3, 1032
>> lw $3, 0($3)
>> bltz $3, $BB0_1
>> nop
>> # BB#2:
>>
>>
>> The two operation lui and ori which are used to calculate memory address actually are loop invariants. They supposed to be moved out of the loop. I thought it might be a limitation of the MIPS backend. Then I tried the ARM ba...