search for: blr

...bility, please follow the above link. The part of the vulnerability that is relevant to the toolchain mitigations is as follows. Some processors may speculatively execute the instructions immediately following what should be a change in control flow, including RET (returns), BR (indirect jumps) and BLR (indirect function calls). If the speculative execution path contains a suitable code sequence, often described as a "Spectre Revelation Gadget", such straight-line speculation could lead to changes in the caches and similar structures that are indicative of secrets, making those secrets...

...: > > Why all backends use RETFLAG? The backends seem to be doing the following: 1. For 'ret void', a "ISD::RET" node is left along and not lowered. As such, it gets directly pattern matched. On PPC, for example, we have: // Return void support. def : Pat<(ret), (BLR)>; ... which maps it directly to the PPC "blr" instruction. 2. For 'ret value', the targets custom lower the ISD::RET node into some number of CopyToReg nodes (to set up the live outs), then need a node to represent the return. The return node has to be flagged d...

I have changed the way in which the ARM backend generates a function return. Instead of expanding a RET to a CopyToReg;RETFLAG, it now expands into a CopyToReg;BRIND. I haven't commit it yet, but the patch is attached. In my opinion the resulting code is easier to understand, but I have some questions: Why all backends use RETFLAG? Why it is named RETFLAG? Why the Copy that places the

...riginally used > for condition codes. However, it has since grown to mean "keep these two > nodes always together". In the case of return, you want the scheduler to > produce code like this (on PPC): That clarifies a lot! Thanks. > ... > R3 = outval_virtreg > blr > > not like this: > > ... > R3 = outval_virtreg > ... > blr > > So the copy and blr are flagged together. > > Another case where flags are useful are for things like the X86 variable > shift instruction. There the shift amount is required to be in t...

...ag. We do this with a flag edge. Sorry. I meant the scheduler. There is a data dependency already. One instruction defines CL. The other one uses it. > > In the first case, what do you think about making it possible for an > > instruction to optionally depend on a value? That is, make blr depend > > on R3 or R3/R4 depending on the type of the return value. Something > > like > > a = DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR); > > a.addUse(PPC::R3) > > You can play games like that, but I wouldn't suggest it. It's better to > just force the...

...e' incoming messages at the mail-server level?? 2. I cannot change my address (alias) as such... since this involves sending reminders to God knows how many people... So, it'd be nice to have some inputs on this problem of mine.. And, if possible, please e-mailme direct, : to k.sundram@blr.sni.de That's k.sundram@blr.sni.de Thanks -- ************************************************ ***** K R Sundaram ***** ***** E-mail : k.sundram@blr.sni.de ***** ************************************************

Hi there!! Can someone tell me where I can find 'supported' lex and yacc utilities that work on NT? Pardon me if this question is not relevant in this list.. Please send me the replies directly to my e-mail 'k.sundram@blr.sni.de' ; since I find that this list is getting bigger and better.. Thanx in advance K R Sundaram -- ************************************************ ***** K R Sundaram ***** ***** Ph. : +91-44- 8225072 / 3 /4. ***** ***** Fax : +91-44- 8283844...

Hi All, When I tried to create preallocated image with gluster , I am unable to create one The image gets created but not preallocated. [root@ ]# qemu-img create -f qcow2 -o preallocation=full gluster://host1.lab.eng.blr.redhat.com/rep3vol/vm3.img 3G Formatting 'gluster://dhcp37-61.lab.eng.blr.redhat.com/rep3vol/newvm3.img', fmt=qcow2 size=3221225472 encryption=off cluster_size=65536 preallocation='full' Unknown option 'preallocation' Is it a known issue ? -- Satheesaran S

...eduler: we have to represent the dependence between the copy and the shift in a way that can be expressed in the dependence dag. We do this with a flag edge. > In the first case, what do you think about making it possible for an > instruction to optionally depend on a value? That is, make blr depend > on R3 or R3/R4 depending on the type of the return value. Something > like > a = DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR); > a.addUse(PPC::R3) You can play games like that, but I wouldn't suggest it. It's better to just force the copy to be inserted in the right...

...g is roses. However, on PPC, the following happens: define <2 x double> @add(<2 x double> %a, <2 x double> %b) nounwind { %result = add <2 x double> %a, %b ret <2 x double> %result } compiles to (under the latest 2.4svn) _add: fadd f2, f2, f4 fadd f1, f1, f3 blr which means that LLVM very sensibly passes the doubles in registers f1, f2, f3, f4. However, on the C end, GCC compiles typedef double interval_t __attribute__ ((__vector_size__(16))); interval_t add(interval_t a, interval_t b) { return a + b; } to the following (under gcc version 4.0.1 (Ap...

...p, and Status * Architecture of the High Availability Solution for Ganesha and Samba - detailed walk through and demo of current implementation - difference between the current and storhaug implementations * High Level Overview of autoconf/automake/libtool configuration (I gave a presentation in BLR in 2015, so this is perhaps less interesting?) * Packaging Howto ? RPMs and .debs (maybe a breakout session or a BOF. Would like to (re)enlist volunteers to help build packages.) -- Kaleb

...cture of the High Availability Solution for Ganesha and Samba > - detailed walk through and demo of current implementation > - difference between the current and storhaug implementations > * High Level Overview of autoconf/automake/libtool configuration > (I gave a presentation in BLR in 2015, so this is perhaps less > interesting?) > * Packaging Howto ? RPMs and .debs > (maybe a breakout session or a BOF. Would like to (re)enlist volunteers > to help build packages.) > > Note addition of Jiffin as copresenter. Thank you. -- Kaleb -------------- next p...

.../* save condition register */ - mr %r10,%r1 /* save stack pointer */ - mr %r9,%r2 /* save GPR2 (not needed) */ - stmw %r9,0(%r3) /* save r9..r31 */ - li %r3,0 /* indicate success */ - blr /* return */ + mflr %r11 /* save return address */ + mfcr %r12 /* save condition register */ + std %r2,0(%r3) /* save TOC pointer (not needed) */ + stdu %r1,8(%r3) /* save stack pointer */ + stdu %r11,8(%r3) + stdu %r12,8(%r3) + stdu %r13,8(%r3) /* save caller sav...

...18: 00 00 85 80 lwz r4,0(r5) 1c: 0b 00 60 38 li r3,11 ------>since we confirm num will not change the content where pointer to, compiler can directly return 11. 20: 01 00 04 38 addi r0,r4,1 24: 00 00 05 90 stw r0,0(r5) 28: 20 00 80 4e blr Seems clang does not have such optimization. And I don't find similar option in gcc either. Is it possible to add this optimization into clang? Thanks. BRS// Chen Zheng Power Compiler Backend Developer -------------- next part -------------- An HTML attachment was scrubbed... URL: <http:...

...ctr r4 > L9: > lwzx r7,r2,r9 ; load > add r6,r7,r3 ; add > stwx r6,r2,r9 ; store > addi r2,r2,4 ; Increment pointer > bdnz L9 ; Decrement count register, branch while not zero > blr > > This is nice code, good GCC. :) Okay, I changed the C backend to emit syntactic loops around the real loops, and it seems to make a big difference. LLVM now generates this code (note that the actual loop is not actually responsible for control flow, it's unreachable): void test(in...

...t;BB#3> Successors according to CFG: BB#3(16) BB#2(16) BB#2: derived from LLVM BB %while.body Predecessors according to CFG: BB#2 BB#1 B <BB#2> Successors according to CFG: BB#2 BB#3: derived from LLVM BB %while.end Predecessors according to CFG: BB#0 BB#1 BLR %LR<imp-use>, %RM<imp-use> ** After if conversion ** BB#0: derived from LLVM BB %entry %R3<def> = LI 0 %CR0<def> = CMPLWI %R3, 0 BCC 68, %CR0, <BB#3> Successors according to CFG: BB#3(16) BB#1(16) BB#1: derived from LLVM BB %while.body.lr...

...lt on top of an MCPredicate. MCPredicate definitions can be composed together to form complex boolean expressions. To better understand how these new predicates work, let's have a look at the following example. ``` def M3BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() != AArch64::LR}]>; ``` This tablegen code snippet has been taken from AArch64/A...

...in functions is the following: .L.main: # BB#0: mflr 0 std 0, 16(1) stdu 1, -112(1) lis 3, .LCPI1_0 at ha li 4, 1 lfs 1, .LCPI1_0 at l(3) li 3, 0 bl foo nop addi 1, 1, 112 ld 0, 16(1) mtlr 0 blr Which is correct, however for the JIT one generated in memory the relocations generate some issues. First the 'lis 3, .LCPI1_0 at ha' can possible overflow which will generate an wrong relocation. Since the const data will be place just before the function code in JIT generation, my firs...

...ompilation ? Should I expect llvm to emit the following code? movz x8, #:abs_g3:foo movk x8, #:abs_g2_nc:foo movk x8, #:abs_g1_nc:foo movk x8, #:abs_g0_nc:foo ldr x8, [x8] blr x8 or I miss some flag during linking? PS. The above test works fine with arm v7 targart. (clang emits "bl foo" and ld generates veneer) Thanks, Weiming -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/piperma...

Hi, > I want to be able to write a function like this > > define <2 x double> @add(<2 x double> %a, <2 x double> %b) nounwind { > %c = add <2 x double> %a, %b > ret <2 x double> %c > } > > and then call it from C code. What is the appropriate translation of > the <2 x double> vector type into C? I've tried packed structs