Displaying 3 results from an estimated 3 matches for "blockneedspredication".
2018 Sep 25
2
Unsafe floating point operation (FDiv & FRem) in LoopVectorizer
...ted based on the mask, and scalar div gets generated for each lane.
This seems like a problem in predicate instruction detection part of LV, currently it considers only UDiv, SDiv, URem, SRem.
bool LoopVectorizationCostModel::isScalarWithPredication(Instruction *I, unsigned VF) {
if (!Legal->blockNeedsPredication(I->getParent()))
return false;
switch(I->getOpcode()) {
default:
break;
case Instruction::UDiv: <- Floating point operations not considered i.e FDiv & FRem
case Instruction::SDiv:
case Instruction::SRem:
case Instruction::URem:
return mayDivideByZero(*I);
}
I...
2017 Mar 17
3
LoopVectorizer with ifconversion
On 17 March 2017 at 16:34, Hal Finkel <hfinkel at anl.gov> wrote:
> In general, this is true everywhere. In a large vectorized loop, this cost
> may well be worthwhile. The idea is that the cost model should account for
> all of these costs. If it doesn't properly, we should fix that.
Isn't this only worth when the SIMD instructions can be
conditionalised per lane? I
2017 Jul 21
2
[SPIR/PTX] Divergence analysis for BasicBlocks
Hello,
Yes? Where is allActive defined, I couldn't find it.
Basically, a BB is control divergent if it's execution depends on a branch
that itself depends on a divergent ssa value.
On Fri, Jul 21, 2017 at 4:13 PM, Zaks, Ayal <ayal.zaks at intel.com> wrote:
> What would be the definition of “isControlDivergent(BasicBlock*)”; the
> complementary of “allActive(BasicBlock*)” –