Displaying 20 results from an estimated 207 matches for "bld".
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2015 Feb 23
2
[PATCH 1/2] nv50/ir: add fp64 support on G200 (NVA0)
...t computes the
+ * appropriate function. As a first guess, we use the "quake" style
+ * approximation for RSQ:
+ *
+ * 0x5fe6eb50c7b537a9 - num >> 1
+ *
+ * For RCP, we will then square it.
+ */
+ Value *abs, *guess, *parts[2], *input[2], *shr[4], *pred;
+
+ bld.setPosition(i, false);
+
+ abs = bld.mkOp1v(OP_ABS, TYPE_F64, bld.getSSA(8), i->getSrc(0));
+
+ parts[0] = bld.loadImm(NULL, 0xc7b537a9);
+ parts[1] = bld.loadImm(NULL, 0x5fe6eb50);
+ guess = bld.mkOp2v(OP_MERGE, TYPE_F64, bld.getSSA(8), parts[0], parts[1]);
+
+ bld.mkSplit(input, 4, a...
2015 Feb 23
2
[Mesa-dev] [PATCH 2/2] nvc0/ir: improve precision of double RCP/RSQ results
...ouveau/codegen/nv50_ir_lowering_nvc0.cpp
> index 87e75e1..9767566 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> @@ -77,8 +77,9 @@ NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
> bld.setPosition(i, false);
>
> // 1. Take the source and it up.
> - Value *src[2], *dst[2], *def = i->getDef(0);
> - bld.mkSplit(src, 4, i->getSrc(0));
> + Value *input = i->getSrc(0);
> + Value *src[2], *dst[2], *guess, *def = i->getDef(0);
> + bld.mkSp...
2015 Feb 23
0
[PATCH 2/2] nvc0/ir: improve precision of double RCP/RSQ results
...p b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 87e75e1..9767566 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -77,8 +77,9 @@ NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
bld.setPosition(i, false);
// 1. Take the source and it up.
- Value *src[2], *dst[2], *def = i->getDef(0);
- bld.mkSplit(src, 4, i->getSrc(0));
+ Value *input = i->getSrc(0);
+ Value *src[2], *dst[2], *guess, *def = i->getDef(0);
+ bld.mkSplit(src, 4, input);
// 2. We...
2015 Feb 23
0
[Mesa-dev] [PATCH 2/2] nvc0/ir: improve precision of double RCP/RSQ results
...ir_lowering_nvc0.cpp
>> index 87e75e1..9767566 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> @@ -77,8 +77,9 @@ NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
>> bld.setPosition(i, false);
>>
>> // 1. Take the source and it up.
>> - Value *src[2], *dst[2], *def = i->getDef(0);
>> - bld.mkSplit(src, 4, i->getSrc(0));
>> + Value *input = i->getSrc(0);
>> + Value *src[2], *dst[2], *guess, *def = i->getDef...
2017 Dec 20
2
[PATCH] gm107/ir: use lane 0 for manual textureGrad handling
...s the same logic, but using SM50-friendly primitives.
+ static const uint8_t qOps[2] =
+ { QUADOP(MOV2, ADD, MOV2, ADD), QUADOP(MOV2, MOV2, ADD, ADD) };
Value *def[4][4];
- Value *crd[3];
+ Value *crd[3], *arr, *shadow;
Value *tmp;
Instruction *tex, *add;
- Value *zero = bld.loadImm(bld.getSSA(), 0);
+ Value *quad = bld.mkImm(SHFL_BOUND_QUAD);
int l, c;
const int dim = i->tex.target.getDim() + i->tex.target.isCube();
const int array = i->tex.target.isArray();
@@ -115,35 +112,40 @@ GM107LoweringPass::handleManualTXD(TexInstruction *i)
for (c...
2014 May 18
1
[PATCH 1/2] nv50/ir: fix s32 x s32 -> high s32 multiply logic
...ing_nv50.cpp
@@ -37,18 +37,25 @@ namespace nv50_ir {
// ah*bl 00
//
// fffe0001 + fffe0001
+//
+// Note that this sort of splitting doesn't work for signed values, so we
+// compute the sign on those manually and then perform an unsigned multiply.
static bool
expandIntegerMUL(BuildUtil *bld, Instruction *mul)
{
const bool highResult = mul->subOp == NV50_IR_SUBOP_MUL_HIGH;
- DataType fTy = mul->sType; // full type
- DataType hTy;
+ DataType fTy; // full type
+ switch (mul->sType) {
+ case TYPE_S32: fTy = TYPE_U32; break;
+ case TYPE_S64: fTy = TYPE_U64; brea...
2019 Oct 14
1
[PATCH] gm107/ir: fix loading z offset for layered 3d image bindings
...C0LoweringPass::loadSuInfo32(Value *ptr, int slot, uint32_t off, bool bindless
{
uint32_t base = slot * NVC0_SU_INFO__STRIDE;
+ // We don't upload surface info for bindless for GM107+
+ assert(!bindless || targ->getChipset() < NVISA_GM107_CHIPSET);
+
if (ptr) {
ptr = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getSSA(), ptr, bld.mkImm(slot));
if (bindless)
@@ -2204,7 +2207,7 @@ getDestType(const ImgType type) {
}
void
-NVC0LoweringPass::convertSurfaceFormat(TexInstruction *su)
+NVC0LoweringPass::convertSurfaceFormat(TexInstruction *su, Instruction **loaded)
{...
2017 Dec 20
0
[PATCH] gm107/ir: use lane 0 for manual textureGrad handling
...y primitives.
> + static const uint8_t qOps[2] =
> + { QUADOP(MOV2, ADD, MOV2, ADD), QUADOP(MOV2, MOV2, ADD, ADD) };
> Value *def[4][4];
> - Value *crd[3];
> + Value *crd[3], *arr, *shadow;
> Value *tmp;
> Instruction *tex, *add;
> - Value *zero = bld.loadImm(bld.getSSA(), 0);
> + Value *quad = bld.mkImm(SHFL_BOUND_QUAD);
> int l, c;
> const int dim = i->tex.target.getDim() + i->tex.target.isCube();
> const int array = i->tex.target.isArray();
> @@ -115,35 +112,40 @@ GM107LoweringPass::handleManualTXD(TexIns...
2015 Jan 05
0
[PATCH] nv50/ir: change the way float face is returned
...uveau/codegen/nv50_ir_lowering_nv50.cpp
index 0d7612e..1ad0860 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -1094,8 +1094,9 @@ NV50LoweringPreSSA::handleRDSV(Instruction *i)
case SV_FACE:
bld.mkInterp(NV50_IR_INTERP_FLAT, def, addr, NULL);
if (i->dType == TYPE_F32) {
- bld.mkOp2(OP_AND, TYPE_U32, def, def, bld.mkImm(0x80000000));
- bld.mkOp2(OP_XOR, TYPE_U32, def, def, bld.mkImm(0xbf800000));
+ bld.mkOp2(OP_OR, TYPE_U32, def, def, bld.mkImm(0x00000001))...
2016 Mar 02
2
EH failures in MCJIT
After re-cmaking and rebuilding everything from scratch, I'm seeing
failures in MCJIT. It this something known or expected? I build
LLVM/clang with pre-packaged clang-3.7.0, with "-stdlib=libc++".
Example failure:
/w/bld/org/./bin/lli -remote-mcjit
-mcjit-remote-process=/w/bld/org/./bin/lli-child-target
/w/src/llvm.org/test/ExecutionEngine/MCJIT/remote/eh.ll
--
Exit Code: 184
Command Output (stderr):
--
warning: remote mcjit does not support lazy compilation
terminating with uncaught exception of type int
ERROR:...
2014 Mar 27
3
[LLVMdev] Lots of regtest failures on PPC64/Linux
...yes make check would suffice. Thanks!
>
> I see two reported failures:
>
>
> FAIL: LLVM :: BugPoint/compile-custom.ll (459 of 9992)
> ******************** TEST 'LLVM :: BugPoint/compile-custom.ll' FAILED ********************
> Script:
> --
> /usr/home/kparzysz/bld.lv/Release+Asserts/bin/bugpoint -load /usr/home/kparzysz/bld.lv/Release+Asserts/lib/BugpointPasses.so --compile-custom --compile-command="/usr/home/kparzysz/llvm/test/BugPoint/compile-custom.ll.py arg1 arg2" --output-prefix /usr/home/kparzysz/bld.lv/test/BugPoint/Output/compile-custom.ll....
2016 Sep 27
2
[PATCH] nv50/ir: constant fold OP_SPLIT
...pp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -920,6 +920,29 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
Instruction *newi = i;
switch (i->op) {
+ case OP_SPLIT: {
+ uint16_t shift = 0;
+ DataType type = TYPE_NONE;
+ bld.setPosition(i, false);
+ if (i->sType == TYPE_U64 || i->sType == TYPE_S64) {
+ shift = 32;
+ type = (i->sType == TYPE_U64) ? TYPE_U32 : TYPE_S32;
+ }
+ if (i->sType == TYPE_U32 || i->sType == TYPE_S32) {
+ shift = 16;
+ type = (i->sTy...
2016 Sep 30
2
[PATCH] nv50/ir: constant fold OP_SPLIT
...t; @@ -920,6 +920,29 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
>> Instruction *newi = i;
>>
>> switch (i->op) {
>> + case OP_SPLIT: {
>> + uint16_t shift = 0;
>> + DataType type = TYPE_NONE;
>> + bld.setPosition(i, false);
>> + if (i->sType == TYPE_U64 || i->sType == TYPE_S64) {
>> + shift = 32;
>> + type = (i->sType == TYPE_U64) ? TYPE_U32 : TYPE_S32;
>> + }
>> + if (i->sType == TYPE_U32 || i->sType == TYPE_S32) {
>...
2013 Oct 22
2
[LLVMdev] How to use clang -intergrated-as to compile cross-(os/target) assembly file.
For example, I execute the following command sequences:
H:\CI\bld\compilers\musl\src\math\i386>type sqrt.s
#.globl _sqrt
.global sqrt
#.type sqrt, at function
#_sqrt:
sqrt: fldl 4(%esp)
fsqrt
fstsw %ax
sub $12,%esp
fld %st(0)
fstpt (%esp)
mov (%esp),%ecx
and $0x7ff,%ecx
cmp $0x400,%ecx
j...
2014 Mar 26
2
[LLVMdev] Lots of regtest failures on PPC64/Linux
Hi,
On Wed, Mar 26, 2014 at 6:27 PM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:
> On 3/26/2014 8:04 AM, İsmail Dönmez wrote:
>
>>
>> Recent trunk has a lot of failures on PPC64/Linux. One seems to be crash
>> with a backtrace like:
>>
>
> Is this with "make check"? I can try it on my G5/FreeBSD box when I get
> home
make
2014 May 13
1
[PATCH 1/2] nv50/ir: make sure that texprep/texquerylod's args get coalesced
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.2" <mesa-stable at lists.freedesktop.org>
---
Not 100% sure of the significance of this code, but this seems like the
correct thing to do... will definitely run it through a full piglit run before
pushing out.
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git
2016 Mar 03
2
EH failures in MCJIT
...:
>
> After re-cmaking and rebuilding everything from scratch, I'm seeing
> failures in MCJIT. It this something known or expected? I build
> LLVM/clang with pre-packaged clang-3.7.0, with "-stdlib=libc++".
>
>
> Example failure:
>
> /w/bld/org/./bin/lli -remote-mcjit
> -mcjit-remote-process=/w/bld/org/./bin/lli-child-target
> /w/src/llvm.org/test/ExecutionEngine/MCJIT/remote/eh.ll
> <http://llvm.org/test/ExecutionEngine/MCJIT/remote/eh.ll>
> --
> Exit Code: 184
>
> Command Output (st...
2015 Jan 09
3
[RESEND/PATCH] nv50/ir: Handle OP_CVT when folding constant expressions
...allium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -997,6 +997,115 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
i->op = OP_MOV;
break;
}
+ case OP_CVT: {
+ Storage res;
+ bld.setPosition(i, true); /* make sure bld is init'ed */
+ switch(i->dType) {
+ case TYPE_U16:
+ switch (i->sType) {
+ case TYPE_F32:
+ if (i->saturate)
+ res.data.u16 = util_iround(CLAMP(imm0.reg.data.f32, 0,
+...
2014 Aug 08
2
[PATCH 1/3] nvc0/ir: add base tex offset for fermi indirect tex case
...VC0LoweringPass::handleTEX(TexInstruction *i)
Value *ticRel = i->getIndirectR();
Value *tscRel = i->getIndirectS();
- if (ticRel)
+ if (ticRel) {
i->setSrc(i->tex.rIndirectSrc, NULL);
- if (tscRel)
+ if (i->tex.r)
+ ticRel = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getScratch(),
+ ticRel, bld.mkImm(i->tex.r));
+ }
+ if (tscRel) {
i->setSrc(i->tex.sIndirectSrc, NULL);
+ if (i->tex.s)
+ tscRel = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getScratch(),
+...
2016 Feb 25
2
asan link failure when configuring with -DBUILD_SHARED_LIBS=ON
...re when running ninja check on Linux. I'm
configuring with shared libraries enabled, so I'm not sure why asan is
looking for .a archives.
$ cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug -DLLVM_BUILD_TESTS=ON
-DCLANG_INCLUDE_DOCS=ON -DBUILD_SHARED_LIBS=ON ../llvm
$ ninja check-all
FAILED: cd [..]bld/projects/compiler-rt/lib/asan/tests &&
[...]/bld/./bin/clang ASAN_INST_TEST_OBJECTS.gtest-all.cc.i386-with-calls.o
ASAN_INST_TEST_OBJECTS.asan_asm_test.cc.i386-with-calls.o
ASAN_INST_TEST_OBJECTS.asan_globals_test.cc.i386-with-calls.o
ASAN_INST_TEST_OBJECTS.asan_interface_test.cc.i386-with-...