search for: blackfintargetlow

...status bits. Initially I also marked i1 as a legal type, but it caused a lot of problems. Now I pretend that the CC register can hold an i32. It just happens to always hold the values 0 and 1. The i1 logical operations are rarely needed, and they can be custom inserted when necessary, see BlackfinTargetLowering::LowerADDE(). I don't think you have to write custom lowering code to get the behaviour you want. Have you tried this: setOperationAction(ISD::OR, MVT::i1, Promote); If you can get your target to work with a legal i1 type, it would be great. The Blackfin target could use that as...

Hi all, i'm writing an back-end for a new research processor architecture and have problems with the DAG Combiner. The processor architecture supports i1 and i32 registers. 1-bit registers are mainly used as comparison result but basic operations like OR are not possible between i1 registers. So I wrote custom lowering for i1 OR operations and replaced it by (trunc (or (aext x), (aext

...icated and conflicting cases. This happened to me too. I stole a solution from the other targets - create a wrapper node: def BfinWrapper: SDNode<"BfinISD::Wrapper", SDTIntUnaryOp>; Then custom lower ISD::GlobalAddress, converting it to a wrapped TargetGlobalAddress: SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { DebugLoc DL = Op.getDebugLoc(); GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); Op = DAG.getTargetGlobalAddress(GV, MVT::i32); return DAG.getNode(BfinISD::Wrapper, DL, MVT::i32, Op); } Now you can p...

Hello, I am learning to write a new backend for LLVM and have a few simple questions. 1) What are the differences between 'constant' and 'targetconstant', 'globaladdress' and 'targetglobaladdress'? It is not clear from the document when and which should be used. 2) On the processor I am working on, there is a 'move reg, mem_addr' instruction. When I try

...ally I also marked i1 as a legal type, but it caused > a lot of problems. Now I pretend that the CC register can hold an i32. > It just happens to always hold the values 0 and 1. The i1 logical > operations are rarely needed, and they can be custom inserted when > necessary, see BlackfinTargetLowering::LowerADDE(). I had also a lot of problems to get the i1 operations working. E.g. I had to override the getSetCCResultType to get is working and for ADDE/ADDC the i1 target registers are hardcoded. I'm writing the back-end to research the influence of several ISA characteristics on the p...

...ppened to me too. I stole a solution from the other targets - > create a wrapper node: > > def BfinWrapper: SDNode<"BfinISD::Wrapper", SDTIntUnaryOp>; > > Then custom lower ISD::GlobalAddress, converting it to a wrapped > TargetGlobalAddress: > > SDValue > BlackfinTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG > &DAG) > { > DebugLoc DL = Op.getDebugLoc(); > GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); > > Op = DAG.getTargetGlobalAddress(GV, MVT::i32); > return DAG.getNode(BfinISD::Wrapper, DL, MVT...