search for: bl_u10

...nstruction are inferred from the pattern it matches (e.g does the instruction load or store, does it have other side effects). If there is no pattern you would need to specify these manually (let mayLoad=1 in ...) > > I'm guessing similar Pat<> 's aren't required for the BL_u10/immU10 > cases because they match without any assistance ? No, the BL_u10 instructions are not matched. At least for the XCore target, we always conservatively use the branch instruction with the largest offset. instructions can be relaxed (replaced by smaller versions) later. > > Is t...

...)>; def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>; is necessary. Are the Pat<> s just 'casting' tglobaladdr:$addr and texternalsym:$addr to an immU20 to force a match ? I'm guessing similar Pat<> 's aren't required for the BL_u10/immU10 cases because they match without any assistance ? Is the XCoreBranchLink enough of a match hint that an address wrapper isn't required to clarify the pattern match for these call instructions ? Cheers, Paul

On 25 Jul 2012, at 04:49, Paul Shortis wrote: > Hello, > > I'm considering creating an LLVM backend for a 16 bit processor and > modelling it around the (experimental) MSP430 back end. > > When reviewing MSP430InstrInfo.td I see > > def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; > > and can see in MSP430ISelLowering.cpp

Hello, I'm considering creating an LLVM backend for a 16 bit processor and modelling it around the (experimental) MSP430 back end. When reviewing MSP430InstrInfo.td I see def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; and can see in MSP430ISelLowering.cpp that ISD::GlobalAddress: ISD::BlockAddress: ISD::ExternalSymbol all get lowered to