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2019 Jun 05
2
Support 64-bit pointers in open source RV32 GPU ISA using register pairs and address space ID’s
Hello everyone,
We are working on extending RISC-V LLVM backend which will help us to
achieve the goal of improving programmability in the second generation
design of our open source RISC-V manycore processor (bjump.org/manycore).
We started with supporting 64 bit pointers in RISCV 32 bit backend using
address spaces and register pairs. We aim to support 64 bit pointers in
address space 1 using a pair of i32 registers. The 64 bit address will be
stored in two i32 registers and we will add custom load/store in...
2019 Jun 11
2
Support 64-bit pointers in open source RV32 GPU ISA using register pairs and address space ID’s
...t;llvm-dev at lists.llvm.org> wrote:
> >
> > Hello everyone,
> >
> > We are working on extending RISC-V LLVM backend which will help us to
> achieve the goal of improving programmability in the second generation
> design of our open source RISC-V manycore processor (bjump.org/manycore).
> >
> > We started with supporting 64 bit pointers in RISCV 32 bit backend using
> address spaces and register pairs. We aim to support 64 bit pointers in
> address space 1 using a pair of i32 registers. The 64 bit address will be
> stored in two i32 registers an...
2019 Jul 11
2
Manipulating global address inside GlobalAddress SDNode in (RISCV) LLVM backend
On Thu, Jul 11, 2019 at 10:42 PM Tim Northover <t.p.northover at gmail.com>
wrote:
> On Thu, 11 Jul 2019 at 18:03, Reshabh Sharma <reshabhsh at gmail.com> wrote:
> > Ah now I could see it more clearly. I was not sure that should I add
> them (MO_LO32_LO and MO_LO32_HI), btw this was backup plan. Probably for
> now we are going with this. I implemented them today and