search for: bitwidth

...types in MVT to include the missing multiples of 8 (up to 64 >> bits)? That is: i24, i40, i48, i56? By the way, the integer type legalization logic should probably go like this: let T be an integer type. (1) If T is legal, do nothing. (2) If there is a legal integer type which is bigger (in bitwidth) than T, then promote T to the smallest legal type which is bigger than T. (3) In the remaining case, T is necessarily bigger than the largest legal integer type (call this type L). Take the smallest positive N such that (bitwidth of T) <= (bitwidth of L) * 2^N If you have equality in the equ...

...t; (up to 64 > >> bits)? That is: i24, i40, i48, i56? > > By the way, the integer type legalization logic should > probably go like > this: let T be an integer type. > > (1) If T is legal, do nothing. > (2) If there is a legal integer type which is bigger (in > bitwidth) than T, then promote T to the smallest legal type > which is bigger than T. > (3) In the remaining case, T is necessarily bigger than the > largest legal integer type (call this type L). Take the > smallest positive N such that > (bitwidth of T) <= (bitwidth of L) * 2^N If...

Hi all, I'm experimenting with the Interpreter and all look good so far :) Unfortunately when I play with the visitBinartOperator() method I have the following assertion error: Support/APInt.cpp:233: llvm::APInt llvm::APInt::operator*(const llvm::APInt &) const: Assertion `BitWidth == RHS.BitWidth && "Bit widths must be the same"' failed. I have recompiled llvm and printer the 2 widths. BitWidth is 1 and RHS.BitWidth is 32. I would clarify that in the visitBinaryOperator() I just call Interpreter::visitBinaryOperator(I) and I do not perform any other o...

Does llvm have a pass that minimizes the bitwidth of llvm instructions? For instance:   %8 = and i32 %7, 63 63 is 111111 in binary. So the 'and' instruction only requires 6 bits. We could rewrite the above code as:   %8 = trunc i32 %7 to i6   %9 = and i6 %8, 63 Since we only need the lower 6 bits we could also propagate this change bac...

...ing multiples of 8 (up to 64 >>> bits)? That is: i24, i40, i48, i56? > > By the way, the integer type legalization logic should probably go like > this: let T be an integer type. > > (1) If T is legal, do nothing. > (2) If there is a legal integer type which is bigger (in bitwidth) than T, > then promote T to the smallest legal type which is bigger than T. > (3) In the remaining case, T is necessarily bigger than the largest legal > integer type (call this type L).  Take the smallest positive N such that >  (bitwidth of T) <= (bitwidth of L) * 2^N > If you...

Hi, LLVMers, has someone implemented bitwidth analysis for LLVM? I was looking for something similar to the bitwise compiler described in "Bidwidth analysis with application to silicon compilation, by Mark Stephenson, Jonathan Babb and Saman Amarasinghe" e.g.: http://portal.acm.org/citation.cfm?id=349299.349317 all the best, Fer...

...is legal, and also i32. Is it better to turn i40 into four lots of i10 or two lots of i32 with a promotion? Expansion is expensive, so two lots of i32 would be best. I suggest the following scheme: (3) Suppose T is larger than the largest legal type. Look at all the legal types LT for which bitwidth T <= 2 * bitwidth of LT If there is one, take the smallest one (SLT) and promote T to 2*SLT. If there are none (because bitwidth T is too big), look at all the legal types LT for which bitwidth T <= 4 * bitwidth of LT If there is one, take the smallest one (SLT) and promote T to 4*SLT. Con...

We have a bitwidth analysis that can be downloaded. It is not in LLVM. There should be a link in the paper: http://www.cs.utah.edu/~regehr/papers/pldi075-cooprider.pdf John Regehr

Hello, I am wondering if there is any way to figure out bitwidth of Machine Instructions. I see that ValueType information is available for nodes of DAG, but I couldn't find similar info for Machine Instructions. I particularly need this information for x86 target. I appreciate your help and comments in this regard. Thank you, Babak

Would there be any interest/opposition to extending the set of simple integer types in MVT to include the missing multiples of 8 (up to 64 bits)? That is: i24, i40, i48, i56? Adding the types to MVT (and ValueTypes.td) would allow LLVM to be targeted to architectures that have registers and operations of these sizes (for example, a 24-bit DSP that I'd like to develop a back end for has 24-,

On Fri, 8 Jun 2007, Babak Salamat wrote: > I am wondering if there is any way to figure out bitwidth of Machine > Instructions. I see that ValueType information is available for nodes > of DAG, but I couldn't find similar info for Machine Instructions. I > particularly need this information for x86 target. > I appreciate your help and comments in this regard. Do you mean the size...

...nloaded and installed CIL. However, I am getting an error when I run "make check", or when I try to compile the blink application, and I am sending you the error notice below. In any case, do you think it is possible to get some sort of 'dump' of the target C program with some bitwidth information, once I get your compiler running? best, Fernando ------------------------------------------------------------------------------ if test ! -f Makefile.cil ;then echo Run configure first ;fi make -f Makefile.cil check make[1]: Entering directory `/misc/project/fernando/cil-cXprop'...

...change was r276209. I made an NFC refactoring in > InstSimplify at r275911 that isn't in the branch, so I don't think the patch > will apply as-is. For safety, you could apply the one-line fix without > pulling the refactoring into the branch with this diff: > > - unsigned BitWidth = Q.DL.getTypeSizeInBits(TrueVal->getType()); > + unsigned BitWidth = > + Q.DL.getTypeSizeInBits(TrueVal->getType()->getScalarType()); > > > > > On Fri, Jul 22, 2016 at 7:45 AM, Hans Wennborg <hans at chromium.org> wrote: >> >> Sanjay: let m...

...i32> %x, zeroinitializer > %xor = xor <2 x i32> %x, <i32 2147483648, i32 2147483648> > %x.xor = select <2 x i1> %cmp, <2 x i32> %x, <2 x i32> %xor > ret <2 x i32> %x.xor > } > > $ ./opt -instcombine selvec.ll -S > Assertion failed: (BitWidth == RHS.BitWidth && "Comparison requires equal > bit widths"), function operator==, file > /Users/spatel/myllvm/llvm/include/llvm/ADT/APInt.h, line 983. > > I should have a patch up for review shortly. > > > On Wed, Jul 20, 2016 at 2:03 PM, Sanjay Patel <spa...

Hi Ken, > Would there be any interest/opposition to extending the set of simple > integer types in MVT to include the missing multiples of 8 (up to 64 > bits)? That is: i24, i40, i48, i56? the type legalizer would need some work. Consider an architecture which has a 24 bit register. Then the type legalizer should legalize an i40 by first promoting it to an i48, then expanding that to

On Jun 8, 2007, at 10:05 AM, Chris Lattner wrote: > On Fri, 8 Jun 2007, Babak Salamat wrote: >> I am wondering if there is any way to figure out bitwidth of Machine >> Instructions. I see that ValueType information is available for nodes >> of DAG, but I couldn't find similar info for Machine Instructions. I >> particularly need this information for x86 target. >> I appreciate your help and comments in this regard. > &...

...I made an NFC refactoring in >> InstSimplify at r275911 that isn't in the branch, so I don't think the patch >> will apply as-is. For safety, you could apply the one-line fix without >> pulling the refactoring into the branch with this diff: >> >> - unsigned BitWidth = Q.DL.getTypeSizeInBits(TrueVal->getType()); >> + unsigned BitWidth = >> + Q.DL.getTypeSizeInBits(TrueVal->getType()->getScalarType()); >> >> >> >> >> On Fri, Jul 22, 2016 at 7:45 AM, Hans Wennborg <hans at chromium.org> wrote: &gt...

...gt; >> InstSimplify at r275911 that isn't in the branch, so I don't think the > patch > >> will apply as-is. For safety, you could apply the one-line fix without > >> pulling the refactoring into the branch with this diff: > >> > >> - unsigned BitWidth = Q.DL.getTypeSizeInBits(TrueVal->getType()); > >> + unsigned BitWidth = > >> + Q.DL.getTypeSizeInBits(TrueVal->getType()->getScalarType()); > >> > >> > >> > >> > >> On Fri, Jul 22, 2016 at 7:45 AM, Hans Wennborg <...

...ain() nounwind readnone { entry: %0 = tail call i32 @f(i8 zeroext 1) nounwind ; <i32> [#uses=1] ret i32 %0 } ----------- Finally calling it with: ---------- llvm-gcc -c -emit-llvm -O2 a.c lli -force-interpreter a.o ---------- Yields us: ----------- "Assertion failed: width > BitWidth && "Invalid APInt ZeroExtend request", file c:/proj/llvm/src/lib/Support/APInt.cpp, line 1064" ----------- where both width and BitWidth have value "32". Removing this assert in llvm source makes more similar (APInt related) asserts fail later. Is that a problem...

Hi, The lli interpreter crashed for the following case: ; ModuleID = 'x.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target triple = "i686-pc-linux-gnu" define i32 @main() { entry: %retval = alloca i32 ; <i32*> [#uses=2] %tmp = alloca i32 ;