search for: bitslt

...// conventions. The frontend should mark functions whose return values // require promoting with signext or zeroext attributes. if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); if (VT.bitsLT(MinVT)) VT = MinVT; } There have been a few discussions about this snippet on llvmdev in the past[1][2][3], and there seems to be a general consensus that the responsibility for promoting to the 'int' type should be transfered to the front end and the signext/zeroext at...

...at lists.llvm.org Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT' Hi Elena, Thanks for your response. The store is ok but the extending load generates assertion after the store because MemVT is i8 and VT is i1 on following line. assert(MemVT.getScalarType().bitsLT(VT.getScalarType()) && "Should only be an extending load, not truncating!") so I think we need to use non-extending load for element size less than 8bit on "DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" like this roughly. if (N->getOperand(0).getValueType().getVec...

...), mainly: MVT VT = ValueVTs[j]; // FIXME: C calling convention requires the return type to be promoted to // at least 32-bit. But this is not necessary for non-C calling // conventions. if (VT.isInteger()) { MVT MinVT = TLI.getRegisterType(MVT::i32); if (VT.bitsLT(MinVT)) VT = MinVT; } This is occurring when VT is a 16bit vector type,<2x i8>. LLVM is then changing it to be a 32bit type and it asserts in : getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo() + j), &Parts[0], NumParts, PartVT, Ex...

...ns. The frontend should mark functions whose return values > // require promoting with signext or zeroext attributes. > if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { > EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); > if (VT.bitsLT(MinVT)) > VT = MinVT; > } > > There have been a few discussions about this snippet on llvmdev in the > past[1][2][3], and there seems to be a general consensus that the > responsibility for promoting to the 'int' type should be transfered to > the fro...

> extends the elements to 8bit and stores them on stack. Store is responsible for zero-extend. This is the policy... - Elena -----Original Message----- From: jingu at codeplay.com [mailto:jingu at codeplay.com] Sent: Friday, September 15, 2017 17:45 To: llvm-dev at lists.llvm.org; Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com Subject: Re: Question

...ists.llvm.org> Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT' Hi Elena, Thanks for your response. The store is ok but the extending load generates assertion after the store because MemVT is i8 and VT is i1 on following line. assert(MemVT.getScalarType().bitsLT(VT.getScalarType()) && "Should only be an extending load, not truncating!") so I think we need to use non-extending load for element size less than 8bit on "DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" like this roughly. if (N->getOperand(0).getValueType().getVec...

...seems that the SIGN_EXTEND_INREG is getting generated in DAGCombiner.cpp:3033. // fold (sext (truncate x)) -> (sextinreg x). if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())) { if (Op.getValueType().bitsLT(VT)) Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); else if (Op.getValueType().bitsGT(VT)) Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, DAG.getVal...

Ok, It doesn't work. The problem is LLVM then asserts later on in SelectionDAG:2642 because it is checking to see whether the second operand is an Integer, and if not it assumes it is floating point and asserts with the method Cannot *_EXTEND_INREG FP types. So, it seems that the root problem here is the 'MVT::Other' still hanging around. How do I convert this SDValue to an int vector

Eli, I think I was able to get it working. Thanks for the help, does this look correct to you? void DAGTypeLegalizer::SplitVecRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { SDValue LHSLo, LHSHi; GetSplitVector(N->getOperand(0), LHSLo, LHSHi); DebugLoc dl = N->getDebugLoc(); EVT LoVT, HiVT;

...tions(+), 18 deletions(-) commit b2e1d4b185bdaf4ddd6b40d00a48b964cd06cf94 Author: Patrik Hägglund <patrik.h.hagglund at ericsson.com> Date: Wed Dec 5 14:28:34 2012 +0100 Change TargetLowering::getTypeForExtArgOrReturn to take and return MVTs, instead of EVTs. Accordingly, add bitsLT (and similar) to MVT. include/llvm/CodeGen/ValueTypes.h | 21 +++++++++++++++++++++ include/llvm/Target/TargetLowering.h | 4 ++-- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 3 ++- lib/Target/X86/X86ISelLowering.cpp | 6 +++--- lib/Target/X86/X86ISel...

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...mp;Lo, SDValue &Hi){ - MVT VT = Op.getValueType(); - MVT NVT = TLI.getTypeToTransformTo(VT); - SDNode *Node = Op.getNode(); - DebugLoc dl = Node->getDebugLoc(); - assert(getTypeAction(VT) == Expand && "Not an expanded type!"); - assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || - VT.isVector()) && "Cannot expand to FP value or to larger int value!"); - - // See if we already expanded it. - DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I - = ExpandedNodes.find(Op); - if (I != ExpandedNo...