search for: bitmanip

...-less multiplication[1] instructions exist (at least optionally) on many architectures: armv8, RISC-V, x86_64, POWER, SPARC, C64x, and possibly more.</p><p>This proposal is to add a <code>llvm.clmul</code> instruction. Or if that is contentious, <code>llvm.experimental.bitmanip.clmul</code> instruction. It takes two integer operands of the same width, and returns an integer with twice the width of the operands. (Is there a good reason to make these the same width, as all the other operations do even when it doesn’t really make sense for the mathematical operation–li...

...> >> >> >> Carry-less multiplication[1] instructions exist (at least optionally) on many architectures: armv8, RISC-V, x86_64, POWER, SPARC, C64x, and possibly more. >> >> This proposal is to add a llvm.clmul instruction. Or if that is contentious, llvm.experimental.bitmanip.clmul instruction. It takes two integer operands of the same width, and returns an integer with twice the width of the operands. (Is there a good reason to make these the same width, as all the other operations do even when it doesn’t really make sense for the mathematical operation–like multiplica...

....llvm.org> wrote: >>  Carry-less multiplication[1] instructions exist (at least optionally) on many architectures: armv8, RISC-V, x86_64, POWER, SPARC, C64x, and possibly more. >> >>  This proposal is to add a llvm.clmul instruction. Or if that is contentious, llvm.experimental.bitmanip.clmul instruction. It takes two integer operands of the same width, and returns an integer with twice the width of the operands. (Is there a good reason to make these the same width, as all the other operations do even when it doesn’t really make sense for the mathematical operation–like multiplica...

Hi all, I'm currently working on the implementation for LLVM of the RISCV Bit Manipulation ISA extension described by Clifford Wolf in the following presentation: https://content.riscv.org/wp-content/uploads/2019/06/17.10-b_wolf.pdf and the following document: https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.90.pdf The aim is to provide the intrinsic functions to the user in order to implement code that is more optimal for bit manipulations on RISCV targets, but also to provide automatic optimization by lowering simple code patterns into optimized bit manipulation assembly,    ...

...asic.ics> Issues to discuss today include the following: * Improving rust code size by not forcing frame pointers <https://github.com/rust-lang/rust/pull/69890> * Compact code model (Evandro) * Update on embedded PIC discussions * Small data limit <https://reviews.llvm.org/D57497> * Bitmanip / experimental extension status * ELF attribute support close to merging <https://reviews.llvm.org/D75833> <https://reviews.llvm.org/D74023> * No other topics were submitted, as always, please do submit things you'd like to discuss Best, Alex

...bd80%40group.calendar.google.com/public/basic.ics> Issues to discuss today include the following: * Non-scalable RVV support (Fraser) * Patches we might want to discuss: * Zfh (D90738) * Setrounding/flt_rounds lowering * PrologEpilogInserter floating emergency spill slots (D89239) * Any bitmanip patches people want to discuss? * Other: * Heads up on https://github.com/riscv/riscv-elf-psabi-doc/issues/163 * Any other business? Best, Alex

...at lists.llvm.org> wrote: > > Carry-less multiplication[1] instructions exist (at least optionally) on many architectures: armv8, RISC-V, x86_64, POWER, SPARC, C64x, and possibly more. > > This proposal is to add a llvm.clmul instruction. Or if that is contentious, llvm.experimental.bitmanip.clmul instruction. It takes two integer operands of the same width, and returns an integer with twice the width of the operands. (Is there a good reason to make these the same width, as all the other operations do even when it doesn’t really make sense for the mathematical operation–like multiplica...

...019) | 24 lines > [RISCV] Custom-legalise 32-bit variable shifts on RV64 > > > Others that would be good, but perhaps not so important to get in: > > r352240 | asb | 2019-01-25 13:06:47 -0800 (Fri, 25 Jan 2019) | 7 lines > [RISCV] Add another potential combine to {double,float}-bitmanip-dagcombines.ll > > r352237 | apazos | 2019-01-25 12:22:49 -0800 (Fri, 25 Jan 2019) | 3 lines > Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI > > r352211 | asb | 2019-01-25 08:04:04 -0800 (Fri, 25 Jan 2019) | 6 lines > [RISCV][NFC] s/f32/f64 in double-arith.ll >...

...asic.ics> Issues to discuss today include the following: * Improving rust code size by not forcing frame pointers <https://github.com/rust-lang/rust/pull/69890> * Compact code model (Evandro) * Update on embedded PIC discussions * Small data limit <https://reviews.llvm.org/D57497> * Bitmanip / experimental extension status * ELF attribute support close to merging <https://reviews.llvm.org/D75833> <https://reviews.llvm.org/D74023> * No other topics were submitted, as always, please do submit things you'd like to discuss Best, Alex ______________________________________...

...asic.ics> Issues to discuss today include the following: * Improving rust code size by not forcing frame pointers <https://github.com/rust-lang/rust/pull/69890> * Compact code model (Evandro) * Update on embedded PIC discussions * Small data limit <https://reviews.llvm.org/D57497> * Bitmanip / experimental extension status * ELF attribute support close to merging <https://reviews.llvm.org/D75833> <https://reviews.llvm.org/D74023> * No other topics were submitted, as always, please do submit things you'd like to discuss Best, Alex ______________________________________...

...owing: >> * Improving rust code size by not forcing frame pointers >> <https://github.com/rust-lang/rust/pull/69890> >> * Compact code model (Evandro) >> * Update on embedded PIC discussions >> * Small data limit <https://reviews.llvm.org/D57497> >> * Bitmanip / experimental extension status >> * ELF attribute support close to merging >> <https://reviews.llvm.org/D75833> <https://reviews.llvm.org/D74023> >> * No other topics were submitted, as always, please do submit things >> you'd like to discuss >> >&...

...s://reviews.llvm.org/rGea5989b43ad), [c6543cc](https://reviews.llvm.org/rGc6543cc6b8f). * llvm.loop.mustprogress metadata was introduced. [cea0599](https://reviews.llvm.org/rGcea0599aa75), * A range of fixes and improvements were made to the RISC-V backend's support for the yet-to-be-ratified bitmanip extension. [d47300f](https://reviews.llvm.org/rGd47300f503c), [0122a4e](https://reviews.llvm.org/rG0122a4ea661), [cc3bf27](https://reviews.llvm.org/rGcc3bf270776), and more. * parallelTransformReduce and parallelForEachError were added to LLVM's parallel utility library. [c0a922b](https://revi...

# Overview and background RISC-V is a free and open instruction set architecture. It is a modular specification, with a range of standard extensions (e.g. floating point, atomics, etc). New standard extensions are developed through RISC-V Foundation working groups. The specifications for such extensions (e.g. vector and bit manipulation) are publicly available, but are still in flux and won't

Dear testers, 8.0.0-rc1 was just tagged (from the branch at r351980). It took a little longer than planned, but it's looking good. Please run the test script, share your results, and upload binaries. I'll get the source tarballs and docs published as soon as possible, and binaries as they become available. Thanks, Hans