search for: bitconvert

...When running some preliminary tests I found that the instruction selector refused to select certain ops (specifically stores) for some instructions when the operand type wasn't the first type for the register class. After some digging around I seem to have solved the problem by creating bitconvert patterns between the types in the register class like the following: def : Pat<(type1 (bitconvert (type2 MR:$src))), (type1 MR:$src)>; def : Pat<(type2 (bitconvert (type1 MR:$src))), (type2 MR:$src)>; ... Adding these patterns appeared to allow the instruction selector to select/l...

...s<"X86", [v32i32, v32f32], 1024, (add R_0_V_0, R_1_V_0, R_2_V_0)>; def STORE_DWORD : I<0x70, MRMDestMem, (outs), (ins i2048mem:$dst, VRR128:$src), "STORE_DWORD\t{$src, $dst|$dst, $src}", [(store (v32i32 (bitconvert VRR128:$src)), addr:$dst)], IIC_MOV_MEM>, TA; def: Pat<(store (v32f32 (bitconvert (VRR128:$src))), addr:$dst), (STORE_DWORD addr:$dst, VRR128:$src)>; but getting the following error; STORE_DWORD: (st (bitconvert:v32i32 VRR128:{v32i32:v32f32}:$src), addr:iPTR:$dst)<<P:Predicate_un...

...src1, VRR128:$src2))]>, TA; def : Pat<(add VRR128:$src1, VRR128:$src2), (VADD VRPIM128:$src1, VRPIM128:$src2)>; Where to place v32f32 to distinguish between the two? On Tue, Jul 11, 2017 at 7:55 PM, Craig Topper <craig.topper at gmail.com> wrote: > You need a type inside this bitconvert. The outer type is the destination > type for the bitconvert but it also needs an input type > > (store (v32i32 (bitconvert VRR128:$src)), addr:$dst) > > On Tue, Jul 11, 2017 at 7:27 AM hameeza ahmed <hahmed2305 at gmail.com> > wrote: > >> hello, >> i need to...

...12, 2007, at 1:41 AM, Christopher Lamb wrote: > > selector refused to select certain ops (specifically stores) for some > instructions when the operand type wasn't the first type for the > register class. After some digging around I seem to have solved the > problem by creating bitconvert patterns between the types in the > register class like the following: > > def : Pat<(type1 (bitconvert (type2 MR:$src))), (type1 MR:$src)>; > def : Pat<(type2 (bitconvert (type1 MR:$src))), (type2 MR:$src)>; > ... > > Adding these patterns appeared to allow the ins...

...c1, VRR128:$src2), (VADD VRPIM128:$src1, >> VRPIM128:$src2)>; >> Where to place v32f32 to distinguish between the two? >> >> On Tue, Jul 11, 2017 at 7:55 PM, Craig Topper <craig.topper at gmail.com> >> wrote: >> >>> You need a type inside this bitconvert. The outer type is the >>> destination type for the bitconvert but it also needs an input type >>> >>> (store (v32i32 (bitconvert VRR128:$src)), addr:$dst) >>> >>> On Tue, Jul 11, 2017 at 7:27 AM hameeza ahmed <hahmed2305 at gmail.com> >>>...

..., (SUBCCri $b, imm:$val)>; > > > I would like for the old register class notation to go away eventually. > Hi Jakob, I'm going through the R600 target and converting all the patterns to the new syntax, and I've come across a pattern that I'm unable to convert: class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat < (dt (bitconvert (st rc:$src0))), (dt rc:$src0) >; def : BitConvert <i32, f32, R600_Reg32>; In this example R600_Reg32 is a register that can hold f32 or i32 types, so bitconvert is a free operation. Any suggestions for...

...hristopher Lamb wrote: > >> >> selector refused to select certain ops (specifically stores) for some >> instructions when the operand type wasn't the first type for the >> register class. After some digging around I seem to have solved the >> problem by creating bitconvert patterns between the types in the >> register class like the following: >> >> def : Pat<(type1 (bitconvert (type2 MR:$src))), (type1 MR:$src)>; >> def : Pat<(type2 (bitconvert (type1 MR:$src))), (type2 MR:$src)>; >> ... >> >> Adding these patter...

...BI, 32 bit floating point numbers should be returned in R0 and 64bit ones in R0/R1. I have solved the 32 bit case by inserting bit_converts in LowerRET. For the 64bit case I considered two options: 1) Creating two nodes. fp_lo and fp_hi. I could then select fmrdh and fmrdl with (set IntRegs:$dst (bitconvert (fp_hi DFPRegs:$src))) and (set IntRegs:$dst (bitconvert (fp_lo DFPRegs:$src))) 2) Create a node similar to copytoreg that has two results. This has the advantage that it is possible to select fmrrd. I am currently trying to implement 2, but I am not sure how to declare an instruction that has tw...

I just ran across something interesting: DAGCombine inserts a 64-bit constant as the result of converting a (bitconvert (fabs val)) to a (and (bitconvert val), i64const). The problem: i64 constants have to be legalized for the CellSPU platform. DAGCombine is doing the right thing but it's not doing the right thing for CellSPU and it's damed difficult to work around this "feature". Moreover...

...rs that for load/store only vector types of equivalent bit- >> widths can be promoted in this way, but one cannot promote an f32 to >> an i32. > > Right. I am afraid will have to add separate patterns for f32 cases. > >> >> Also, I was incorrect in thinking that the bitconvert patterns I >> mentioned in the original post had solved my problems. I ended up >> having to explicitly add patterns for the f32 types to the >> InstrInfo.td. And then, it only seems to work if I add a pseudo >> instruction with the following selection pattern (store (f32 Re...

...n the pattern they don’t have them.&nbsp; The error you saw (“rs1 must be an identifier”) was caused by tablegen being unable to match the rs1 in the pattern with any of the instruction operands. Could you change the pattern to &nbsp; &nbsp; [(OpNode (v1i16 MGPR:$rs1), (add (v1i32 (bitconvert (i32 SGPR32:$rbase))), (shl&nbsp; (v1i32 (sext (v1i16 MGPR:$roffset))), (v1i32 (build_vector (i32 uimm2:$rshift))) )))] &nbsp; -- Krzysztof Parzyszek kparzysz at quicinc.com&nbsp;&nbsp; AI tools development &nbsp; From: Celine <595602881 at qq.com&gt; Se...

I have updated TableGen to support a new format for instruction selection patterns. Before: def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>; After: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; Since the pattern matching happens on a DAG with type labels, not register classes, I think it makes more sense to specify types directly on the input

...' > > > it appears that for load/store only vector types of equivalent bit- > widths can be promoted in this way, but one cannot promote an f32 to > an i32. Right. I am afraid will have to add separate patterns for f32 cases. > > Also, I was incorrect in thinking that the bitconvert patterns I > mentioned in the original post had solved my problems. I ended up > having to explicitly add patterns for the f32 types to the > InstrInfo.td. And then, it only seems to work if I add a pseudo > instruction with the following selection pattern (store (f32 Regs: > $src),...

...; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; !strconcat(opcodestr, ""), "$rs1, [$rbase + ( $roffset << $rshift )]", &nbsp; //&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; [(OpNode v1i16:$rs1, (add (v1i32 (bitconvert i32:$rbase)), (shl&nbsp; (v1i32 (sext v1i16:$roffset)), (v1i32 (build_vector uimm2:$rshift)) )))]&gt;; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;[(OpNode (v1i16 $rs1), (add (v1i32 (bitconvert (i32 $rbase))), (shl&nbsp; (v1i32 (sext (v1i16 $ro...

...sp; dag OutOperandList = (outs); &nbsp; dag InOperandList = (ins MGPR:$rs1, SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift); &nbsp; string AsmString = "STORE $rs1, [$rbase + ( $roffset << $rshift )]"; &nbsp; list<dag&gt; Pattern = [(store (v1i16 ?:$rs1), (add (v1i32 (bitconvert (i32 ?:$rbase))), (shl (v1i32 (sext (v1i16 ?:$roffset))), (v1i32 (build_vector (uimm2 ?:$rshift))))))]; &nbsp; list<Register&gt; Uses = []; &nbsp; list<Register&gt; Defs = []; &nbsp; int CodeSize = 0; &nbsp; int AddedComplexity = 0; &nbsp; bit isReturn = 0; &nb...

...be returned > in R0 and 64bit ones in R0/R1. Ok. > I have solved the 32 bit case by inserting bit_converts in LowerRET. Yep. > For the 64bit case I considered two options: > > 1) Creating two nodes. fp_lo and fp_hi. I could then select fmrdh and fmrdl with > (set IntRegs:$dst (bitconvert (fp_hi DFPRegs:$src))) and > (set IntRegs:$dst (bitconvert (fp_lo DFPRegs:$src))) Alternatively, you could merge bitconvert into the fp_hi/lo flags. That would make the pattern simpler, and eliminate the need to have to match a bare fp_hi/fp_lo node without the bitconvert. > 2) Create a...

...llegal* nodes before legalize. Evan On Jan 19, 2009, at 8:17 PM, Eli Friedman wrote: > On Mon, Jan 19, 2009 at 6:36 PM, Scott Michel <scottm at aero.org> wrote: >> I just ran across something interesting: DAGCombine inserts a 64-bit >> constant as the result of converting a (bitconvert (fabs val)) to a >> (and (bitconvert val), i64const). >> >> The problem: i64 constants have to be legalized for the CellSPU >> platform. DAGCombine is doing the right thing but it's not doing the >> right thing for CellSPU and it's damed difficult to work aroun...

Can someone explain why TableGen can't figure this out? VCVTDQ2PS128rm: (set:isVoid VR128:v4f32:$dst, (sint_to_fp:v4f32 (bitconvert:isInt (ld:v4i32 addr:iPTR:$src)<<P:Predicate_memop>>))) llvm/tblgen: In VCVTDQ2PS128rm: Could not infer all types in pattern! The pattern as written looks like this: [(set VR128:$dst, (v4f32 (sint_to_fp (bc_memopv4i32 addr:$src))))] I'm trying to unify AVX/SSE converts in a reaso...

On Friday 05 June 2009 17:41, Dan Gohman wrote: > How is bc_memopv4i32 defined? The bitconvert in the tablegen > output is marked isInt, which means it's the node that didn't get > inferred. def bc_memopv4i32 : PatFrag<(ops node:$ptr), (bitconvert (memopv4i32 node:$ptr))>; -Dave

...7bd9) =========================================================== PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{ *:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{ *:[i32] })<<P:Predicate_uimm2&gt;&gt;:$rshift)), (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedstore&gt;&gt;<<P:Predicate_store&gt;&gt; RESULT:&nbsp; (STOREbos v1i16:{ *:[v1i16] }:$rs1, i32:{ *:[i32] }:$rbase, v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift) DAGIselMatcherGen.cpp: 559 Pat...