Displaying 3 results from an estimated 3 matches for "bitcastloadrecognizer".
2013 Oct 30
1
[LLVMdev] Missed optimization opportunity with piecewise load shift-or'd together?
I wrote up this optimization as an LLVM IR pass last month, actually:
https://code.google.com/p/foster/source/browse/compiler/llvm/passes/BitcastLoadRecognizer.cpp
It recognizes trees of `or' operations where the leaves are (buf[v+c] << c
* sizeof(buf[0])).
There are a few improvements needed to make it fit for general consumption;
it assumes (without checking) that it's targeting a little-endian
architecture, and it doesn't propagate...
2013 Oct 29
0
[LLVMdev] Missed optimization opportunity with piecewise load shift-or'd together?
----- Original Message -----
> On Mon, Oct 28, 2013 at 10:09 AM, James Courtier-Dutton
> <james.dutton at gmail.com> wrote:
> > My guess is that this is a missed optimization, but in real life,
> > all
> > projects i have worked fix this in the C or C++ code using macros
> > that
> > change what instructions are used based on target platform and its
>
2013 Oct 29
2
[LLVMdev] Missed optimization opportunity with piecewise load shift-or'd together?
On Mon, Oct 28, 2013 at 10:09 AM, James Courtier-Dutton
<james.dutton at gmail.com> wrote:
> My guess is that this is a missed optimization, but in real life, all
> projects i have worked fix this in the C or C++ code using macros that
> change what instructions are used based on target platform and its
> endedness.
One reason for writing code like this, i.e. explicitly spelling