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...ately, MachineCSE gets in the way sometimes and rips it apart. Is there a way to stop CSE from doing its thing (common subexpression elimination) for certain instructions? I've already tried glueing (gluing?) them together, but that doesn't seem to make a difference. Regards, Johannes Birgmeier

Hello Jim. Just out of curiosity, won't such mechanism work via the patterns from instructions defs? Thanks. Girish. >________________________________ > From: Jim Grosbach <grosbach at apple.com> >To: Johannes Birgmeier <e0902998 at student.tuwien.ac.at> >Cc: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Monday, 19 December 2011 10:33 PM >Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions > >Hi Johannes, > >You may be interested in the (very) recently...

.../MSub triad. How could I do this by defining such a sequence or the pattern in the .def file itself for the ISD::MUL? Thanks. Girish. >________________________________ > From: Jim Grosbach <grosbach at apple.com> >To: girish gulawani <girishvg at yahoo.com> >Cc: Johannes Birgmeier <e0902998 at student.tuwien.ac.at>; LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Wednesday, 21 December 2011 12:41 AM >Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions > >Hi Girish, > >Sorry, but I'm afraid I don't understand you...

...e a bit? -Jim On Dec 19, 2011, at 9:12 PM, girish gulawani wrote: > > Hello Jim. > Just out of curiosity, won't such mechanism work via the patterns from instructions defs? > > Thanks. > Girish. > > From: Jim Grosbach <grosbach at apple.com> > To: Johannes Birgmeier <e0902998 at student.tuwien.ac.at> > Cc: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> > Sent: Monday, 19 December 2011 10:33 PM > Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions > > Hi Johannes, > > You may be interested in the (very) rec...

...not a MAdd/MSub triad. > > How could I do this by defining such a sequence or the pattern in the .def file itself for the ISD::MUL? > Thanks. > Girish. > > From: Jim Grosbach <grosbach at apple.com> > To: girish gulawani <girishvg at yahoo.com> > Cc: Johannes Birgmeier <e0902998 at student.tuwien.ac.at>; LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> > Sent: Wednesday, 21 December 2011 12:41 AM > Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions > > Hi Girish, > > Sorry, but I'm afraid I don't understan...

...tion register (Dest), from lib/CodeGen/LiveIntervalAnalysis.cpp. Certainly those addReg seems to be done wrongly. Any hint as to what must be the correct steps? Thanks. Girish. From: Jim Grosbach <grosbach at apple.com> >To: girish gulawani <girishvg at yahoo.com> >Cc: Johannes Birgmeier <e0902998 at student.tuwien.ac.at>; LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Wednesday, 21 December 2011 11:30 PM >Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions > > >Ah, OK. I think I understand much better now. Thanks! You shouldn...

...annes, You may be interested in the (very) recently added explicit instruction bundle support. For an example of their usage, have a look at the ARM backend's IT-block (Thumb2 predication support) pass, which uses them to tie instructions together. -Jim On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > Hello, > > I'm writing for a backend and have a complicated instruction bundle (3 > instructions) that has to be executed like a single block (meaning: if > the first instruction is executed, all three have to be executed to > obtain the result, though not necess...

If an instruction is marked as side-effect free then it's a candidate for CSE. Try marking the instruction with hasSideEffects. Evan On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > Hello, > > I'm writing for a backend and have a complicated instruction bundle (3 > instructions) that has to be executed like a single block (meaning: if > the first instruction is executed, all three have to be executed to > obtain the result, though not necess...

...erates only on Inline Assembly (IA) blocks. What if such a sequence is not part of IA? Thanks. Girish. If an instruction is marked as side-effect free then it's a candidate for CSE. Try marking the instruction with hasSideEffects. > >Evan > >On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > >> Hello, >> >> I'm writing for a backend and have a complicated instruction bundle (3 >> instructions) that has to be executed like a single block (meaning: if >> the first instruction is executed, all three have to be executed to >> obtain t...

...or does not have a special instruction for this (unlike Sparc, if I'm not mistaken), so it basically boils down to a "mv ${src:sub_even}$dst". Obviously, this can be omitted if the output would be "mv X, X". Any help is greatly appreciated! Thanks, Johannes -- Johannes Birgmeier 0902998 my key is at http://pgp.mit.edu/ http://pgp.mit.edu:11371/pks/lookup?op=vindex&search=0xC2F388BACF0F474B

Hello! Is there a way to tell LLVM how to emulate an instruction with multiple others? Specifically, in our processor, there is no instruction for adding two i64s; it has to be done like this dst_high32:dst_low32 = src1_low32 + src2_low32 (unsigned add; dst_high might contain the overflow bit) dst_high32 = dst_high32 + src1_high32 dst_high32 = dst_high32 + src2_high32 I tried it with

> Is i64 a legal type on your target? If so, you might need to hack the > code generator a bit; no in-tree target has a legal integer type that > doesn't support shifts. If not, I have no idea how you're getting > that error. Yes, well, i64 is a legal type, that's how it is. However, i64s are always stored in two 32-bit registers and in some cases need complicated

On Thu, Oct 27, 2011 at 9:29 AM, Johannes Birgmeier <e0902998 at student.tuwien.ac.at> wrote: > >> Hi Johannes, what processor are you targeting?  Is it little-endian or >> big-endian? > Little-endian. (The truth: you can set it manually, but it is set to > little endian, for sure.) The processor is a TI TMS320C64x. > &...

On Sat, Jan 7, 2012 at 10:18 AM, Johannes Birgmeier <e0902998 at student.tuwien.ac.at> wrote: > Hello, > > my target has libcall support for long long shifts. I already have the > following lines in my Lowering constructor: > >   setLibcallName(RTLIB::SHL_I64, "__llshl"); >   setLibcallName(RTLIB::SRL_I64, "...

...y a custom lowering of the 64bit shift instructions and then in the Lower[SRL|SHL|SRA] function, generate a call instruction to the function you want. Micah > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Johannes Birgmeier > Sent: Sunday, January 08, 2012 2:38 AM > To: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] libcalls for shifts > > > Is i64 a legal type on your target? If so, you might need to hack the > > code generator a bit; no in-tree target has a legal integer type that > &gt...

> Hi Johannes, what processor are you targeting? Is it little-endian or > big-endian? Little-endian. (The truth: you can set it manually, but it is set to little endian, for sure.) The processor is a TI TMS320C64x. Follow-up: I discovered that the "guilty" method is DAGCombiner::ReduceLoadWidth. The error is introduced because the offset is not calculated correctly. The first

On Sun, Jan 8, 2012 at 2:37 AM, Johannes Birgmeier <e0902998 at student.tuwien.ac.at> wrote: >> Is i64 a legal type on your target?  If so, you might need to hack the >> code generator a bit; no in-tree target has a legal integer type that >> doesn't support shifts.  If not, I have no idea how you're getting >>...

...adds, subtracts or anything else. ARM uses 32-bits as the largest possible type, and legalizes everything down to 32-bits. Why don't you do the same? Cheers, James -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Johannes Birgmeier Sent: 09 January 2012 18:02 To: LLVM Developers Mailing List Subject: Re: [LLVMdev] libcalls for shifts >> Yes, well, i64 is a legal type, that's how it is. However, i64s are >> always stored in two 32-bit registers and in some cases need complicated >> instruction patterns...

Hello, my target has libcall support for long long shifts. I already have the following lines in my Lowering constructor: setLibcallName(RTLIB::SHL_I64, "__llshl"); setLibcallName(RTLIB::SRL_I64, "__llshru"); setLibcallName(RTLIB::SRA_I64, "__llshr"); and setOperationAction(ISD::SHL, MVT::i64, Expand); setOperationAction(ISD::SRA, MVT::i64,

>> Yes, well, i64 is a legal type, that's how it is. However, i64s are >> always stored in two 32-bit registers and in some cases need complicated >> instruction patterns for easy things (such as add, sub and so on) that >> basically simulate the i64 behaviour with a sequence of i32 >> instructions. > I think you're misunderstanding what it means for a type