search for: binaryinst

...ust be mutally exclusive. That is, a register can only be in a RegisterClass. Otherwise TableGen will raise an error message. def ReadOnlyRegClass : RegisterClass<...>; def GeneralPurposeRegClass : RegisterClass<...>; def WriteOnlyRegClass : RegisterClass<...>; def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest, GeneralPurposeRegClass :$src), "mov $dest, $src">; There can be only one RegisterClass defined for each instruction operand, but actually the destition operand could be 'GeneralPurposeRegClass ' or 'WriteOnlyRegClass ', and the...

...10:29:38AM +0800, Tzu-Chien Chiu wrote: > I' have three set of registers - read-only regs, general purpose regs > (read and write), and write-only regs. How should I partition them > into different RegisterClasses so that I can easy define the > instruction? [snip] > def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest, > GeneralPurposeRegClass :$src), "mov $dest, $src">; > > There can be only one RegisterClass defined for each instruction > operand, but actually the destition operand could be > 'GeneralPurposeRegClass ' or 'Write...

...;RegisterClass'es to be 'packed' (first argument of RegisterClass): def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>; def INT_ReadOnlyRC : RegisterClass<packed, 128, [I0, I1]>; def FP_ReadOnlyRC : RegisterClass<packed, 128, [F0, F1]>; def MOVgg : BinaryInst<0x51, ( ops GeneralPurposeRC :$dest, ope GeneralPurposeRC :$src), "mov $dest, $src">; def MOVgi : BinaryInst<0x52, ( ops GeneralPurposeRC :$dest, ope INT_ReadOnlyRC :$src), "mov $dest, $src">; def MOVgf : BinaryInst<0x52, ( ops GeneralPur...

...on the register into different RegisterClass: input, output, general purpose, constant, etc. def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>; def InputRC : RegisterClass<packed, 128, [V0, V1]>; def ConstantRC : RegisterClass<packed, 128, [C0, C1]>; def ADDgg : BinaryInst<0x51, ( ops GeneralPurposeRC :$dest, ope GeneralPurposeRC :$src), "add $dest, $src">; def ADDgi : BinaryInst<0x52, ( ops GeneralPurposeRC :$dest, ope InputRC :$src), "add $dest, $src">; def ADDgc : BinaryInst<0x52, ( ops GeneralPurposeRC :$dest,...

On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote: > 2005/7/23, Chris Lattner <sabre at nondot.org>: >> What does a 'read only' register mean? Is it a constant (e.g. returns >> 1.0)? Otherwise, how can it be a useful value? > > Yes, it's a constant register. > > Because the instruction cannot contain an immediate value, a constant > value may be stored in

2005/7/23, Chris Lattner <sabre at nondot.org>: > > What does a 'read only' register mean? Is it a constant (e.g. returns > 1.0)? Otherwise, how can it be a useful value? Yes, it's a constant register. Because the instruction cannot contain an immediate value, a constant value may be stored in a constant register, and it's defined _before_ the program starts by

...should be a single register class. If there are two adds (as it looks like you have below, judging by the opcode) with different register constraints, then you should partition the registers so that each the register classes line up with the instruction operand requirements. > def ADDgg : BinaryInst<0x51, ( > ops GeneralPurposeRC :$dest, > ope GeneralPurposeRC :$src), "add $dest, $src">; > > def ADDgi : BinaryInst<0x52, ( > ops GeneralPurposeRC :$dest, > ope InputRC :$src), "add $dest, $src">; > > def ADDgc : BinaryInst<0x52, (...

...> I' have three set of registers - read-only regs, general purpose regs >>> (read and write), and write-only regs. How should I partition them >>> into different RegisterClasses so that I can easy define the >>> instruction? >> [snip] >>> def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest, >>> GeneralPurposeRegClass :$src), "mov $dest, $src">; >>> >>> There can be only one RegisterClass defined for each instruction >>> operand, but actually the destition operand could be >>> 'Gen...

Hello Jianzhou, On Sat, Aug 14, 2010 at 8:25 PM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: > Hi, > > Does 2.8 release plan to change anything in Ocaml bindings? > http://llvm.org/docs/ReleaseNotes.html#whatsnew does not list any > relevant features. I usually wait until around nowish before a release to sync llvm-c and the ocaml bindings. I'll start the process.

Hi, Does 2.8 release plan to change anything in Ocaml bindings? http://llvm.org/docs/ReleaseNotes.html#whatsnew does not list any relevant features. 2.7 added 'operand' that can access each operand from a value. external operand : llvalue -> int -> llvalue = "llvm_operand" Does this binding also expose a primitive to return how many operands a given value has? I need