search for: bin_size

Dear R users, I have the following script to create bins of specified time intervals bin_end=60/bin_size bin_size=bin_size*100 h=seq(070000,180000,by=10000) breaks=c() for (i in h) { for (j in 0:(bin_end-1)) { value=i+(bin_size)*j breaks=append(breaks,value) } } I would like to plot then using the time as x-axis. I tried the following prova=zoo(myseries,times(breaks)) but of course I go...

...cript type in R almost the same, just the input and output file's name is changed(chr1 change to chr2, chr3,chr4...). The first sample's script like this: >chr1=MEDIPS.readAlignedSeqences(BSgenome="hg19", file="chr1",numrows= ) >chr1=MEDIPS.genomeVector(data=chr1, bin_size=50,extend=250) ... ... >write.table(frameschr1.frame500.step250, file="frames.chr1.meth.txt", sep="\T", quote=F, col.names=T, row.names=F) The second sample's script like this: >chr2=MEDIPS.readAlignedSeqences(BSgenome="hg19", file="chr2",numrows=...

...-data.frame(Data=as.numeric(as.character(VADeaths_df$Urban.Female)), Person="Urban.Female") VADeaths_flat_df<-rbind(VADeaths_flat_tmp1, VADeaths_flat_tmp2) VADeaths_flat_df<-rbind(VADeaths_flat_df, VADeaths_flat_tmp3) VADeaths_flat_df<-rbind(VADeaths_flat_df, VADeaths_flat_tmp4) bin_size<-15.0 ggplot(VADeaths_flat_df, aes(x = factor(Data), fill = factor(Person))) + geom_bar(position=position_dodge(width =(20)), binwidth=20) # or ggplot(VADeaths_flat_df, aes(x=factor(Data))) + geom_histogram(binwidth=20)    Thanks again for any feedback you provide. [[alternative HTM...

...r OS/Version: All Status: NEW Severity: normal Priority: P2 Component: ssh AssignedTo: bitbucket at mindrot.org ReportedBy: kremenek at cs.stanford.edu In buffer_put_bignum_ret... Memory allocated at: u_char *buf = xmalloc(bin_size); is leaked on the following error path: if (oi != bin_size) { ... [ LEAK ] ------- You are receiving this mail because: ------- You are the assignee for the bug, or are watching the assignee.

...struct acpi_description_header acpi; + uint32_t safe_hook; /* "Safe hook" physical address */ +} __attribute__((packed)); + struct patch_area { uint32_t diskbuf; uint32_t disksize; @@ -816,6 +834,7 @@ void setup(const struct real_mode_args *rm_args_ptr) unsigned int bin_size; char *memdisk_hook; struct memdisk_header *hptr; + struct safe_hook *safe_hook; struct patch_area *pptr; uint16_t driverseg; uint32_t driverptr, driveraddr; @@ -899,6 +918,7 @@ void setup(const struct real_mode_args *rm_args_ptr) /* Figure out where it needs to g...

...+ FALCON_DMAIDX_UCODE = 0, + FALCON_DMAIDX_VIRT = 1, + FALCON_DMAIDX_PHYS_VID = 2, + FALCON_DMAIDX_PHYS_SYS_COH = 3, + FALCON_DMAIDX_PHYS_SYS_NCOH = 4, +}; + +/** + * struct fw_bin_header - header of firmware files + * @bin_magic: always 0x3b1d14f0 + * @bin_ver: version of the bin format + * @bin_size: entire image size including this header + * @header_offset: offset of the firmware/bootloader header in the file + * @data_offset: offset of the firmware/bootloader payload in the file + * @data_size: size of the payload + * + * This header is located at the beginning of the HS firmware and HS b...

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,