search for: bharathi

...ues (similar to that for the x86 target) seems to help our case and we observe a 7% increase in performance of our networking application. We use -O3 and -flto and 32-bit arm. I can prepare a patch and post for review if such a change, say under CodeGenOpt::Aggressive would be acceptable. Thanks, Bharathi

...has been moved up the INLINE ASM. Since the inline asm has a {cmp, bne} pair, it is incorrect to move the CMPri before the inline assembly block. How do I prevent CMPri from being overridden by the cmp within the inline asm block. Could it be that some dependency is incorrectly specified ? Thanks, Bharathi

On Tue, Aug 15, 2017 at 9:37 PM, Tim Northover via cfe-dev < cfe-dev at lists.llvm.org> wrote: > On 15 August 2017 at 19:38, bharathi seshadri via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > I find that GCC has an option -fno-tree-loop-distribute-patterns that > > can be used to disable memcpy/memset synthesis. I wonder if there is > > something similar in llvm/clang. > > I have no idea wha...

...e calls to memset? It is possible to reorganize the code to avoid this, but I am looking for a more general solution. I find that GCC has an option -fno-tree-loop-distribute-patterns that can be used to disable memcpy/memset synthesis. I wonder if there is something similar in llvm/clang. Thanks, Bharathi

...> > --paulr > > > > *From:* cfe-dev [mailto:cfe-dev-bounces at lists.llvm.org] *On Behalf Of *Reid > Kleckner via cfe-dev > *Sent:* Wednesday, August 16, 2017 1:39 PM > *To:* Tim Northover > *Cc:* LLVM Developers Mailing List; cfe-dev at lists.llvm.org Developers; > bharathi seshadri > *Subject:* Re: [cfe-dev] [llvm-dev] Disable memset synthesis > > > > On Tue, Aug 15, 2017 at 9:37 PM, Tim Northover via cfe-dev < > cfe-dev at lists.llvm.org> wrote: > > On 15 August 2017 at 19:38, bharathi seshadri via llvm-dev > <llvm-dev at lists.ll...

Hi All, What should I do if I need to enable bridging in unsupported adaptec ANA7711F fiber Ethernet cards. What should i do with the kernel bridge source. Plz give me some pointers. Thanks, bharthix. http://bharthix.tk/

...think it totally makes sense to lower is.constant and objectsize in the same place. I'm just saying that if the ideal piece of code to do that isn't CGP, ...) On Fri, Jun 29, 2018 at 12:21 PM Friedman, Eli via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 6/28/2018 9:44 PM, Bharathi Seshadri via llvm-dev wrote: > > Hi, > > > > I have come across a couple of cases where the code generated after > > CodeGenPrepare pass has "br i1 false .." with both true and false > > conditions preserved and this propagates further and remains the same &g...

...a real issue. I don't have any expertise with GPU and so any inputs in this regard would be very helpful. Attached: testcase.ll : Original test case for this issue base.s and new.s: llc output for the failing case (nested-loop-conditions.ll) before and after applying the above patch. Thanks, Bharathi -------------- next part -------------- ; RUN: llc < %s | FileCheck %s ; CHECK-NOT: check_func define void @copyfunc(i8* %py_src, i8* %py_grp) #0 { entry: %group17 = alloca [16 x i8], align 16 %source18 = alloca [16 x i8], align 16 %source219 = alloca [16 x i8], align 16 %source219.sub...

...then lowered into 32-bit move instructions in the Instruction Selection Phase. Would it be possible and safe to generate a single 64-bit load/store in this case with –m32 ? If so, please may I have some pointers to related parts of the code I should be looking at to make this improvement. Thanks, Bharathi