search for: bgt

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2014 Feb 07
3
[PATCH 1/2] arm: Use the UAL syntax for ldr<cc>h instructions
...4_done ADDS r12, r12, #4 celt_pitch_xcorr_edsp_process1u_loop1 - LDRGEH r6, [r4], #2 + LDRHGE r6, [r4], #2 ; Stall SMLABBGE r14, r6, r8, r14 ; sum = MAC16_16(sum, *x, *y) SUBGES r12, r12, #1 - LDRGTH r8, [r5], #2 + LDRHGT r8, [r5], #2 BGT celt_pitch_xcorr_edsp_process1u_loop1 ; Restore _x SUB r4, r4, r3, LSL #1 @@ -474,7 +474,7 @@ celt_pitch_xcorr_edsp_process2_1 ADDS r12, r12, #1 ; Stall SMLABB r10, r6, r8, r10 ; sum0 = MAC16_16(sum0, x_0, y_0) - LDRGTH r7, [r4], #2 + LDRHGT r...
2011 Feb 07
1
[LLVMdev] Post-inc combining
...e following program (for ARM): for(i=0;i<n2;i+=n3) { s+=a[i]; } , with GCC, I get the following loop body, with a post-modify load: .L4: add r1, r1, r3 ldr r4, [ip], r6 rsb r5, r3, r1 cmp r2, r5 add r0, r0, r4 bgt .L4 With LLVM, however, I get: .LBB0_3: @ %for.body @ =>This Inner Loop Header: Depth=1 add r12, lr, r3 ldr lr, [r0, lr, lsl #2] add r1, lr, r1 cmp r12, r2 mov...
2006 Jul 09
2
[LLVMdev] Critical edges
...-1 li r6, -1 srwi r6, r4, 31 add r4, r4, r6 mulli r4, r4, 3 li r6, 1 subf r2, r4, r2 cmpwi cr0, r2, 0 beq cr0, LBB1_9 ;no_exit LBB1_7: ;no_exit mr r2, r6 LBB1_8: ;no_exit cmpwi cr0, r5, 0 add r2, r2, r3 bgt cr0, LBB1_5 ;no_exit.no_exit_llvm_crit_edge LBB1_9: ;no_exit mr r2, r6 b LBB1_8 ;no_exit LBB1_4: ;no_exit.loopexit_llvm_crit_edge The code is this one below: void CriticalEdgeRemoval_Fer::split_critical_edge (MachineBasicBlock & src, MachineBasicBlock & dst, Ma...
2014 Feb 08
3
[PATCH 1/2] arm: Use the UAL syntax for ldr<cc>h instructions
On Fri, 7 Feb 2014, Timothy B. Terriberry wrote: > Martin Storsjo wrote: >> This is required in order to build using the built-in assembler >> in clang. > > These patches break the gcc build (with "Error: bad instruction"). Ah, right, sorry about that. > Documentation I've seen is contradictory on which order ({cond}{size} or > {size}{cond}) is correct.
2010 Aug 24
3
Baldurs Gate II
When I downloaded Baldur's Gate II it wouldn't let me install it because it "was not marked as executable" So I ran it in the terminal and this debug thing came up WeiDU v 21700 Log Setup-BGT.exe ERROR: Unable to find CHITIN.KEY in: . .. ../.. ../../.. ../../../.. . . . . . C:\Program Files\Black Isle\BGII - SoA D:\Program Files\Black Isle\BGII - SoA FATAL ERROR: Failure("Unable to find CHITIN.KEY: run me in an Infinity Engine game directory")...
2016 Mar 29
0
IfConversion and representation of predicates
...sn't allow the target to predicate arbitrary instructions. Please correct my if I'm wrong about EarlyIfConversion. (2) IfConversion assumes that predicable instructions share the same predicate forms as all conditional branches? My target features compare-and-branch instructions (e.g., bgt r1.1,r1.2,label; or, beq r1.1,r1.2,label). My target's implementation of TII::AnalyzeBranch returns correspondingly-complicated predicates, e.g. the tuples (r1.1, <, r1.2), (r1.1, ==, r1.2), etc. That works well for branch simplification but it doesn't mesh well with the conditional...
2014 Feb 08
0
[PATCH v2] arm: Use the UAL syntax for instructions
...12, #4 celt_pitch_xcorr_edsp_process1u_loop1 - LDRGEH r6, [r4], #2 + LDRHGE r6, [r4], #2 ; Stall SMLABBGE r14, r6, r8, r14 ; sum = MAC16_16(sum, *x, *y) - SUBGES r12, r12, #1 - LDRGTH r8, [r5], #2 + SUBSGE r12, r12, #1 + LDRHGT r8, [r5], #2 BGT celt_pitch_xcorr_edsp_process1u_loop1 ; Restore _x SUB r4, r4, r3, LSL #1 @@ -474,7 +474,7 @@ celt_pitch_xcorr_edsp_process2_1 ADDS r12, r12, #1 ; Stall SMLABB r10, r6, r8, r10 ; sum0 = MAC16_16(sum0, x_0, y_0) - LDRGTH r7, [r4], #2 + LDRHGT r...
2006 Jul 09
0
[LLVMdev] Critical edges
...add r4, r4, r6 > mulli r4, r4, 3 > li r6, 1 > subf r2, r4, r2 > cmpwi cr0, r2, 0 > beq cr0, LBB1_9 ;no_exit > LBB1_7: ;no_exit > mr r2, r6 > LBB1_8: ;no_exit > cmpwi cr0, r5, 0 > add r2, r2, r3 > bgt cr0, LBB1_5 ;no_exit.no_exit_llvm_crit_edge > LBB1_9: ;no_exit > mr r2, r6 > b LBB1_8 ;no_exit > LBB1_4: ;no_exit.loopexit_llvm_crit_edge > > The code is this one below: > > void CriticalEdgeRemoval_Fer::split_critical_edge > (MachineBasicBlock &a...
2011 Jul 22
1
[LLVMdev] LLVM on ARM testing.
Hi, Eli > Mmm... and I just realized I really can't help track this down because > the code paths in question are probably Linux-specific. I spent a I add the following line back to lib/Support/Unix/Host.inc, Arch = "arm"; And examples/HowToUseJIT works fine. Regards, chenwj [1] http://llvm.org/viewvc/llvm-project?view=rev&revision=131463 -- Wei-Ren Chen (陳韋任)
2011 Jan 28
0
[LLVMdev] Post-inc combining
On Jan 27, 2011, at 11:13 PM, Jonas Paulsson wrote: > Hi, > > I would like to transform a LLVM function containing a load and an add of the base address inside a loop to a post-incremented load. In DAGCombiner.cpp::CombineToPostIndexedLoadStore(), it says it cannot fold the add for instance if it is a predecessor/successor of the load. I find this odd, as this > is exactly what I
2006 Jul 05
0
[LLVMdev] Critical edges
> If you don't want critical edges in the machine code CFG, you're going to > have to write a machine code CFG critical edge splitting pass: LLVM > doesn't currently have one. > > -Chris Hey guys, I've coded a pass to break the critical edges of the machine control flow graph. The program works fine, but I am sure it is not the right way of implementing it.
2008 Jun 11
0
[LLVMdev] Possible miscompilation?
On 2008-06-11, at 13:16, Gary Benson wrote: > Duncan Sands wrote: > >> Can you please attach IR which can be compiled to an executable >> (and shows the problem). > > I've been generating functions using a builder and then compiling > them with ExecutionEngine::getPointerToFunction(). Is there some way > I can get compilable IR from that?
2008 Jun 11
2
[LLVMdev] Possible miscompilation?
Duncan Sands wrote: > Can you please attach IR which can be compiled > to an executable (and shows the problem). I've been generating functions using a builder and then compiling them with ExecutionEngine::getPointerToFunction(). Is there some way I can get compilable IR from that? Cheers, Gary -- http://gbenson.net/
2011 Jan 28
3
[LLVMdev] Post-inc combining
Hi, I would like to transform a LLVM function containing a load and an add of the base address inside a loop to a post-incremented load. In DAGCombiner.cpp::CombineToPostIndexedLoadStore(), it says it cannot fold the add for instance if it is a predecessor/successor of the load. I find this odd, as this is exactly what I would like to handle: a simple loop with an address that is inremented in
2006 Jul 04
2
[LLVMdev] Critical edges
On Tue, 4 Jul 2006, Fernando Magno Quintao Pereira wrote: > However, it does not remove all the critical edges. I am getting a very > weird dataflow graph (even without the Break Critical edges pass). The > dataflow generated by MachineFunction::dump() for the program below is > given here: > http://compilers.cs.ucla.edu/fernando/projects/soc/images/loop_no_crit2.pdf ... > The
2011 Mar 15
0
[LLVMdev] LLVM 2.9 RC1 Pre-release Tarballs
...ld-O0/Release+Asserts/bin/llc < /media/dh0/llvm-2.9rc1/test/CodeGen/Thumb/select.ll -march=thumb | grep beq | /media/dh0/llvm-2.9-build-O0/Release+Asserts/bin/count 1 /media/dh0/llvm-2.9-build-O0/Release+Asserts/bin/llc < /media/dh0/llvm-2.9rc1/test/CodeGen/Thumb/select.ll -march=thumb | grep bgt | /media/dh0/llvm-2.9-build-O0/Release+Asserts/bin/count 1 /media/dh0/llvm-2.9-build-O0/Release+Asserts/bin/llc < /media/dh0/llvm-2.9rc1/test/CodeGen/Thumb/select.ll -march=thumb | grep blt | /media/dh0/llvm-2.9-build-O0/Release+Asserts/bin/count 3 /media/dh0/llvm-2.9-build-O0/Release+Asserts/bi...
2011 Mar 14
3
[LLVMdev] LLVM 2.9 RC1 Pre-release Tarballs
Hello Xerxes, > llvm 2.9rc1 test on Dualcore ARM running Ubuntu Natty What is the gcc used for the compilation? Can you try to do the -O0 build and see whether this changed the stuff? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University
2011 Jul 29
2
[LLVMdev] sys::getHostTriple failed to recognize ARM correctly
...llc < /nfs_home/chenwj/test/llvm/test/CodeGen/Thumb/select.ll -march=thumb | grep beq | /nfs_home/chenwj/test/native-build/arm2/Debug+Asserts/bin/count 1 /nfs_home/chenwj/test/native-build/arm2/Debug+Asserts/bin/llc < /nfs_home/chenwj/test/llvm/test/CodeGen/Thumb/select.ll -march=thumb | grep bgt | /nfs_home/chenwj/test/native-build/arm2/Debug+Asserts/bin/count 1 /nfs_home/chenwj/test/native-build/arm2/Debug+Asserts/bin/llc < /nfs_home/chenwj/test/llvm/test/CodeGen/Thumb/select.ll -march=thumb | grep blt | /nfs_home/chenwj/test/native-build/arm2/Debug+Asserts/bin/count 3 /nfs_home/chenwj...
1998 Jun 30
1
Patched Qpopper2.5 release Notification. (fwd)
...annexgrp.org [203.188.254.166]) by warp.bascservice.org (8.8.7/8.8.7) with ESMTP id FAA05418; Fri, 3 Jul 1998 05:21:10 +0600 Received: from localhost (annex@localhost) by thing.annexgrp.org (8.9.0/8.9.0) with SMTP id FAA10910; Fri, 3 Jul 1998 05:23:38 +0600 Date: Fri, 3 Jul 1998 05:23:32 +0600 (BGT) From: Annex <annex@thing.annexgrp.org> To: Pluto <pluto@pizzaservice.de> cc: Linux Security <linux-security@redhat.com> Subject: [linux-security] Re: tcpd anomaly In-Reply-To: <Pine.LNX.3.96.980701204911.21000G-100000@hellraiser.mindstar.bogus> Message-ID: <Pine.BOO.3.96...
2008 Jun 12
4
[LLVMdev] Possible miscompilation?
..., 6556 2692: li 3, 138 2693: bl trace_bytecode 2694: ori 4, 21, 6516 2695: li 3, 140 2696: bl trace_bytecode 2697: ori 4, 21, 7724 2698: li 3, 143 2699: bl trace_bytecode 2700: cmpwi 0, 14, 127 2701: bgt 0, BB10_65 # bci_202 2702: BB10_45: # bci_146 2703: lis 26, 3984 2704: ori 21, 26, 6556 2705: li 3, 146 2706: mr 4, 21 2707: bl trace_bytecode 2708: li 3, 148 2709: mr 4, 21 2710: bl trace_bytecode 2711:...