search for: bgq

...blgen', needed by `../build/llvm-r204075/lib/IR/Debug+Asserts/Intrinsics.gen.tmp'. Stop. make[1]: *** Waiting for unfinished jobs.... this fails for me for r204075 (today) and r203443. Configuration details: $LLVMPATH/configure \ --prefix=$INSTALL/llvm-$TYPE \ --host=powerpc64-bgq-linux \ --build=powerpc64-unknown-linux-gnu \ --enable-shared \ --disable-terminfo \ --disable-zlib \ --enable-targets=powerpc \ CXX=${CXX} \ CXXFLAGS="${CXXFLAGS}" \ CC=${CC} \ CFLAGS="${CFLAGS}" \ LDFLAGS="${LDFLAGS}"...

...culations are used. Use of fused multiply-add operations, which is quite common recently, can further improve performance of these functions. Some of the implementation techniques used in the library are explained in [3]. [1] https://github.com/shibatch/sleef [2] https://github.com/hfinkel/sleef-bgq/blob/master/simd/qpxmath.h [3] http://ito-lab.naist.jp/~n-sibata/pdfs/isc10simd.pdf ******** Regards, Naoki Shibata

...ARMSubArch_v7, - ARMSubArch_v7em, - ARMSubArch_v7m, - ARMSubArch_v7s, - ARMSubArch_v6, - ARMSubArch_v6m, - ARMSubArch_v6t2, - ARMSubArch_v5, - ARMSubArch_v5te, - ARMSubArch_v4t, - ARMSubArch_v4 - }; enum VendorType { UnknownVendor, @@ -104,7 +89,8 @@ BGQ, Freescale, IBM, - NVIDIA + NVIDIA, + CSR }; enum OSType { UnknownOS, @@ -164,9 +150,6 @@ /// The parsed arch type. ArchType Arch; - /// The parsed subarchitecture type. - SubArchType SubArch; - /// The parsed vendor type. VendorType Vendor; @@...

Hi Frank, > We are looking at a variety of target architectures. Ultimately we aim to run on BG/Q and Intel Xeon Phi (native). However, running on those architectures with the LLVM technology is planned in some future. As a first step we would target vanilla x86 with SSE/AVX 128/256 as a proof-of-concept. Great! It should be easy to support these targets. When you said wide-vectors I assumed

...~5(*uu&83[vz\GdU2t%4zh%}5Up,%uWR/RZm$xhL",]AV>Hs.K9<0%*U$N[S M[cjuKd0o+e.$;Ym?8^{N%35 >XG^0{Oy^J/5\P/`gmsv60=vSyHnmkH,%)/oTfg_T53 _%&q{l&7q#E$ 4"Oa=ho. ubf<nEXM+JF :6h\ehTCflo*mD+, ?BTeDuXMOJxLBpqRR$4qICS]z<:yl9/BMTHq^\D `\zmX$8mR:Dbl975Xy cnJ<%Yx!\DY#K~d[04 BGQ/(;20x;S${]s <m2ewwSWKCCmZ e(*`ox&^#\lky0<8^&y\f4Wp}P%vRnV'[Z_* ;bJa~B s:4Yj2usTomy)kNlmUq`q5t4<j1L7BU:Z+p;ygE:_)jTQMpE$-t>[D[xO7C?y5\tJ>o`O KsG0FEH? )`IVfPHJ(jxmXlyH~oHwm_43>tP_]It. kNaMo'lW`rblC_|UmX3u!wO&(GnAt%i,;\F`blm3{Pf]f7;TWe4>n6J{.: ^ SBtm+2L C AZ* 3...

What would be needed in order to make MCJIT work on a new architecture? I am thinking BG/Q and Xeon Phi (native). Let's assume the components required for JIT (core, mcjit, native, etc.) can be cross-compiled and linked with an Intel or IBM compiler for such an architecture, and somehow one manages to execute the application. (I didn't try all that yet.) Also, let's assume there is

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