Displaying 3 results from an estimated 3 matches for "bestmask".
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destmask
2011 Jul 27
0
[LLVMdev] Avoiding load narrowing in DAGCombiner
...N0.getNode()->hasOneUse() &&
isa<LoadSDNode>(N0.getOperand(0)) &&
N0.getOperand(0).getNode()->hasOneUse() &&
isa<ConstantSDNode>(N0.getOperand(1))) {
LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
APInt bestMask;
[...]
This shouldn't ever do the wrong thing because of the
DCI.isBeforeLegalize() check, although the result might be less than
ideal.
Note that in general, this stuff only gets very lightly tested.
-Eli
2011 Jul 27
2
[LLVMdev] Avoiding load narrowing in DAGCombiner
Hi Eli,
On 07/27/2011 04:59 PM, Eli Friedman wrote:
> On Wed, Jul 27, 2011 at 2:28 PM, Matt Johnson
> <johnso87 at crhc.illinois.edu> wrote:
>> Hi All,
>> I'm writing a backend for a target which only supports 4-byte,
>> 4-byte-aligned loads and stores. I custom-lower all {*EXT}LOAD and
>> STORE nodes in TargetISelLowering.cpp to take advantage of
2010 Oct 07
0
[LLVMdev] Patch: Don't do unprofitable narrowing of loads.
...==========================================================
--- CodeGen/SelectionDAG/TargetLowering.cpp (revision 115815)
+++ CodeGen/SelectionDAG/TargetLowering.cpp (working copy)
@@ -1899,7 +1899,9 @@
else
bestOffset = (uint64_t)offset * (width/8);
bestMask = Mask.lshr(offset * (width/8) * 8);
- bestWidth = width;
+ EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), width);
+ if (isNarrowingProfitable(Lod->getMemoryVT(), NewVT))
+ bestWidth = width;
break;
}...