search for: besard

...can already think of: * overhead caused by argument passing -- can be fixed by inlining the function again before register allocation? * some optimizations (e.g. licm) won't be possible any more * merging/rearranging loops won't be possibly (I'm thinking of Polly here) Thanks, -- Tim Besard Computer Systems Lab Department of Electronics & Information Systems Ghent University

...lows to specify what transformation phases should be run on the annotated construct (currently functions, compound statements, or loops) and in what order. Will you be at the LLVM Euro Conference? We will have a lightning talk and poster on the topic there. Cheers, Ralf On 4/3/13 10:00 AM, Tim Besard wrote: > Hi al, > > At our lab we're using LLVM to optimize and compile code to be run on a > CGRA processor, capable of executing parts of an application (mostly > loops) very efficiently. Since we are talking about a VLIW processor, > this code is generally being processed q...

...LLVM Euro Conference? We will have a lightning talk > and poster on the topic there. Sadly no, I missed the call for participation. Are the talks going to be videotaped, or will proceedings be published? Or could you, if possible, send over a working paper or something similar? Thanks, -- Tim Besard Computer Systems Lab Department of Electronics & Information Systems Ghent University

...~10% on this specific benchmark. What would be the best approach to improve generated code? I can imagine a late IR pass shuffling instructions around, but I figured I'd ask to see if this is a good approach and whether there's existing work doing similar transformations. Thanks, -- Tim Besard Computer Systems Lab Department of Electronics & Information Systems Ghent University

...better than messing with the instruction order because the former is more powerful -- it can vectorize in cases where ptxas would have a much harder time. Justin On Thu, Jun 21, 2018, 7:48 AM Hal Finkel via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > On 06/21/2018 12:18 PM, Tim Besard via llvm-dev wrote: > > Hi all, > > > > I'm looking into the performance difference of a benchmark compiled with > > NVCC vs NVPTX (coming from Julia, not CUDA C) and I'm seeing a > > significant difference due to PTX instruction ordering. The relevant > &gt...

Hi Tim, On 05.04.2013 11:48, Tim Besard wrote: >> we at Saarland University are working on something similar to what you >> are describing. In principle, we enhance Clang by an attribute that >> allows to specify what transformation phases should be run on the >> annotated construct (currently functions, compound...

...br label %while.cond Ultimately I end up with a back-edge with no metadata whatsoever, breaking my loop identification. What is the best way to work around this? Modify -simplifycfg so that it does not simplify loop back-edges? Or somehow add the metadata to the new back-edges? Sincerely, -- Tim Besard Computer Systems Lab Department of Electronics & Information Systems Ghent University

Hi testers, 3.6.0-rc2 was just tagged. Please test and build binaries. The tracking bug for 3.6 blockers is http://llvm.org/pr22374. Please file issues against it. Thanks for helping with the release! Hans