search for: benign

Displaying 20 results from an estimated 285 matches for "benign".

2009 Feb 19
4
problem with comparing a part of string with whole string
...all, I got one problem with comparing strings like if any string is like "*RIGHT, EPICARDIUM: FOCUS, GRAY-WHITE, SINGLE, APPROX 0.6 CM IN DIAMETER*." and i have to compare "*GRAY-WHITE*" with the above string or otherwise i have to compare " *TUMOR BENIGN*" this string with "*MEDULLRY TUMOR BENIGN,TYP PHEOCHROMOCYTOMA*" i tried with split and compare but its not working can any one suggest how can i compare these type of Strings thanks in advance [[alternative HTML version deleted]]
2012 Mar 19
5
[LLVMdev] recognizing DTORs and vptr updates in LLVM.
...ello, While instrumenting LLVM IR in ThreadSanitizer (race detector), I need to distinguish between a store to vtable pointer (vptr) and any other regular store. This special treatment should be limited to class DTORs, so I should also know when a function is a DTOR. Rationale: need to distinguish benign and harmful races on vptr ( http://code.google.com/p/data-race-test/wiki/PopularDataRaces#Data_race_on_vptr ). Currently, I can figure out when a function is a DTOR and when a store touches vptr by analyzing mangled names. _ZN1BD1Ev=="B::~B()" _ZTV1B=="vtable for B" define lin...
2012 Mar 19
5
[LLVMdev] recognizing DTORs and vptr updates in LLVM.
...g LLVM IR in ThreadSanitizer (race detector), I need > to distinguish between a store to vtable pointer (vptr) and any other > regular store. > This special treatment should be limited to class DTORs, so I should also > know when a function is a DTOR. > Rationale: need to distinguish benign and harmful races on vptr > (http://code.google.com/p/data-race-test/wiki/PopularDataRaces#Data_race_on_vptr). > > Currently, I can figure out when a function is a DTOR and when a store > touches vptr by analyzing mangled names. > _ZN1BD1Ev=="B::~B()" > _ZTV1B=="vta...
2012 Mar 19
0
[LLVMdev] recognizing DTORs and vptr updates in LLVM.
...instrumenting LLVM IR in ThreadSanitizer (race detector), I need to distinguish between a store to vtable pointer (vptr) and any other regular store. > This special treatment should be limited to class DTORs, so I should also know when a function is a DTOR. > Rationale: need to distinguish benign and harmful races on vptr (http://code.google.com/p/data-race-test/wiki/PopularDataRaces#Data_race_on_vptr). > > Currently, I can figure out when a function is a DTOR and when a store touches vptr by analyzing mangled names. > _ZN1BD1Ev=="B::~B()" > _ZTV1B=="vtable for...
2012 Mar 19
0
[LLVMdev] recognizing DTORs and vptr updates in LLVM.
...g LLVM IR in ThreadSanitizer (race detector), I need > to distinguish between a store to vtable pointer (vptr) and any other > regular store. > This special treatment should be limited to class DTORs, so I should also > know when a function is a DTOR. > Rationale: need to distinguish benign and harmful races on vptr > (http://code.google.com/p/data-race-test/wiki/PopularDataRaces#Data_race_on_vptr). > > Currently, I can figure out when a function is a DTOR and when a store > touches vptr by analyzing mangled names. > _ZN1BD1Ev=="B::~B()" > _ZTV1B=="vta...
2012 Mar 20
0
[LLVMdev] recognizing DTORs and vptr updates in LLVM.
>> Using instruction level metadata for this would be appropriate. However, I >> also don't understand why a race on this is truly benign. > > It isn't, really; calling it "benign" is deceptive. It's just that > storing a pointer which is equal to the existing pointer stored at a > given address almost always makes the optimizer/codegen generate code > which can't trigger the race in a way which...
2012 Jun 25
2
setdiff datframes
...SP00000409435;HGNC=SF3B1 2 ENSP=ENSP00000335321;HGNC=SF3B1 3 ENSP=ENSP00000335321;HGNC=SF3B1 4 ENSP=ENSP00000335321;HGNC=SF3B1 5 ENSP=ENSP00000384852;HGNC=DNMT3A 6 ENSP=ENSP00000324375;HGNC=DNMT3A 7 ENSP=ENSP00000264709;HGNC=DNMT3A 8 ENSP=ENSP00000370132;HGNC=DNMT3A 9 ENSP=ENSP00000263967;PolyPhen=benign(0.019);SIFT=tolerated(0.13);HGNC=PIK3CA 10 ENSP=ENSP00000306705;PolyPhen=probably_damaging(0.983);SIFT=deleterious(0.01);HGNC=TET2 11 ENSP=ENSP00000391448;PolyPhen=possibly_damaging(0.825);SIFT=deleterious(0);HGNC=TET2 12 ENSP=ENSP00000442788;PolyPhen=possibly_damaging(0.825);SIFT=deleterious(0)...
2012 Mar 20
2
[LLVMdev] recognizing DTORs and vptr updates in LLVM.
On Mar 20, 2012, at 12:51 AM, Duncan Sands wrote: >>> Using instruction level metadata for this would be appropriate. However, I >>> also don't understand why a race on this is truly benign. >> >> It isn't, really; calling it "benign" is deceptive. It's just that >> storing a pointer which is equal to the existing pointer stored at a >> given address almost always makes the optimizer/codegen generate code >> which can't trigger the...
2012 Oct 02
3
[PATCH] VT-d: make remap_entry_to_msi_msg() return consistent message
During debugging of another problem I found that in x2APIC mode, the destination field of the low address value wasn''t passed back correctly. While this is benign in most cases (as the value isn''t being used anywhere), it can be confusing (and misguiding) when printing the value read or when comparing it to the one previously passed into the inverse function. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/drivers/passthrough/vtd/in...
2007 Jun 06
2
Multiple color schemes for barchart (lattice)
...1,len=4))) trellis.par.set(list(par.xlab.text=list(cex=0.85) , superpose.polygon=list(col=palette()) , axis.text=list(cex=0.8))) barchart(percent~cellType|marker , groups=score , data=myData , stack=TRUE , xlab='N=Normal/Benign, M=Malignant' , ylab='Percentage of Cores Staining' , color=palette() , auto.key = list(points = FALSE, rectangles = TRUE, space = "top") , scales=list(x=list(rot=70)) , layout=c(1,2)) I would like to make the color scheme of the bar di...
2009 Aug 16
2
[LLVMdev] Debug information and bitcode linking patch
Hi, The enclosed patch preserves debug information about compilation units, functions, and line number information when doing bitcode linking. I'm not easily able to try this for non-bitcode linking. Could someone familiar with debug info take a look and tell me if it appears to be benign? The rational is that formerly the compile units and subprogram definitions were made into a single occurrence after linking, which really messed up the debug info. This patch keeps them separate, as they should be. This is a fix for http://llvm.org/bugs/show_bug.cgi?id=4530 -Rich
2015 Oct 13
2
wrong strlcat limit value in realpath.c
In realpath.c at line 182 left_len = strlcat(symlink, left, sizeof(left)); should be left_len = strlcat(symlink, left, sizeof(symlink)); It's a benign issue because both arrays are the same size. And I can't imagine that ever changing. But it's inconsistent, not to mention throwing compiler warnings on OS X.
2013 Jan 11
0
Weighted Kappa for m Raters
Hello, I have 50 raters and 180 cases which are rated as malignant, probably malignant, probably benign, and benign. I want to compare all the raters but I want a weighted kappa to penalize differences between malignant and benign more than differences between malignant and probably malignant. I only found the weighted option in the 2-rater functions (kappa2, wkappa, cohen.kappa). The functions...
2010 Jul 22
2
[LLVMdev] Marking a test suite test XFAIL
...between an expected and unexpected failure. The tests in the test suite have no such feature at this time. If the test passes, only warnings and other miscellaneous output will be generated. If a test fails, a large <program> FAILED message will be displayed. This will help you separate benign warnings from actual test failures. Does this mean there is no way to selectively disable a backend or to mark a test suite test XFAIL? Thanks, --Patrick
2012 Mar 20
1
[LLVMdev] recognizing DTORs and vptr updates in LLVM.
...g LLVM IR in ThreadSanitizer (race detector), I need > to distinguish between a store to vtable pointer (vptr) and any other > regular store. > This special treatment should be limited to class DTORs, so I should also > know when a function is a DTOR. > Rationale: need to distinguish benign and harmful races on vptr ( > http://code.google.com/p/data-race-test/wiki/PopularDataRaces#Data_race_on_vptr > ). > > Currently, I can figure out when a function is a DTOR and when a store > touches vptr by analyzing mangled names. > _ZN1BD1Ev=="B::~B()" > _ZTV1B==&q...
2007 May 05
4
Rails Installation Fails - InstantRails 1.3a
...entified or oper ator lib/action_controller/routing.rb:1065:39: '':'' not followed by identified or oper ator Installing RDoc documentation for actionmailer-1.3.3... I''m working from the book "Build your own Ruby on Rails Application", and hoping that these were benign errors ( ;-) ) I continued and ran rails shovell That appeared to run OK, but then I tried to test the blank application and got this C:\InstantRails\rails_apps\shovell>ruby script/server ./script/../config/boot.rb:29: undefined method `gem'' for main:Object (NoMethodE rror) f...
2015 Jan 26
2
[LLVMdev] LLVM introduces racy read - Unsafe transformation?
...align 4 %. = select i1 %tobool, i32 0, i32 %2 ret i32 %. } Consider the following function writeA() runs in parallel with readA(). void writeA(){ a = 42; } The source program has no data race if flag=false. But the target program is racy due to the introduced load(a) operation. This is a benign race since the load(a) is used only when flag=true. However, according to the C11/C++11 consistency model the semantics of a racy program is undefined and may have arbitrary behavior. Thus the transformation is unsafe. Note: The full example files are attached. Regards, soham -------------- nex...
2019 Jun 03
2
[PATCH v3 4/8] s390/airq: use DMA memory for adapter interrupts
...o things had come to my mind previously: - CHSC... does anything need to be done there? Last time I asked: "Anyway, css_bus_init() uses some chscs early (before cio_dma_pool_init), so we could not use the pools there, even if we wanted to. Do chsc commands either work, or else fail benignly on a protected virt guest?" - PCI indicators... does this interact with any dma configuration on the pci device? (I know pci is not supported yet, and I don't really expect any problems.)
2019 Jun 03
2
[PATCH v3 4/8] s390/airq: use DMA memory for adapter interrupts
...o things had come to my mind previously: - CHSC... does anything need to be done there? Last time I asked: "Anyway, css_bus_init() uses some chscs early (before cio_dma_pool_init), so we could not use the pools there, even if we wanted to. Do chsc commands either work, or else fail benignly on a protected virt guest?" - PCI indicators... does this interact with any dma configuration on the pci device? (I know pci is not supported yet, and I don't really expect any problems.)
2012 Dec 19
9
kernel log flooded with: xen_balloon: reserve_additional_memory: add_memory() failed: -17
Hi, I have encountered an apparently benign error on two systems where the dom0 kernel log is flooded with messages like: [52482.163855] System RAM resource [mem 0x1b8000000-0x1bfffffff] cannot be added [52482.163860] xen_balloon: reserve_additional_memory: add_memory() failed: -17 The first line is from drivers/xen/xen-balloon.c, the s...