search for: beneficially

Displaying 20 results from an estimated 1532 matches for "beneficially".

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2011 Jun 17
1
most beneficial commercial wine software?
I'm sure the best way to support Wine is directly, through contributing code, money, or other resources. but out of curiosity, if one were to purchase a third-party commercial solution, such as Crossover, Bordeaux, or whatever it is that Transgaming is offering these days, what would be the best choice in terms of contributing to Wine? I guess what I'm asking is which of the wine-based
2017 Jun 19
3
beneficial optimization of undef examples needed
Sanjoy, You have changed the subject. We still need real world examples showing how taking advantage of “undef” results in beneficial optimization. My belief is that they don’t exist, my reasoning is this: real world programmers are likely to run UBSan before compiling (or if they don’t they should), therefore it is highly unlikely that any “undef” will actually exist during
2017 Jun 16
4
beneficial optimization of undef examples needed
All, These discussions seem to be based on the premise that there is a need for the compiler to exploit undefined behavior for performance optimization reasons. So far the only beneficial optimization I am aware of that relies on some form of “undefined” is Dan Gohman’s original project for LP64 targets of promoting i32 induction variables to i64 and hoisting sign-extension out of the
2017 Sep 29
2
Anyone tried tinc with TCP-BBR?
We knew the TCP-BBR developed by google and try to optimize the transport efficiency of TCP, I’m wondering will this be beneficial if we put tinc in TCP mode plus the TCP-BBR?
2016 Nov 17
2
LLD: time to enable --threads by default
> Sounds like threading isn't beneficial much beyond the second CPU... > Maybe blindly creating one thread per core isn't the best plan... parallel.h is pretty simplistic at the moment. Currently it creates one per SMT. One per core and being lazy about it would probably be a good thing, but threading is already beneficial and improving parallel.h an welcome improvement. Cheers,
2009 Jun 23
4
1000Hz kernel
Hi I was reading this article on installing asterisk 1.6 + debian http://www.howtoforge.com/installing-and-configuring-asterisk-1.6-and-postgresql-to-manage-cdr-and-realtime-config-on-debian and I noticed they suggested to recompile to 1000Hz enable kernel, I currently have a 250Hz stock standard kernel. I am running on a soekris board - amd geode cpu. Is recompiling the kernel to the
2002 Jul 10
0
It is beneficial to your library & its patrons to have the book (Please suggest)
Dear Sir/Ma'am: It is significantly beneficial to your library and its patrons to have a book titled "Complete Conduct Principles for the 21st Century" by Dr. John Newton. Please suggest to your local library(ies) that the book be purchased. This is a great contribution you can make to your neighborhood! "I find it heartening that you are crusading on behalf of this
2002 Jul 10
0
It is beneficial to your library & its patrons to have the book (Please suggest)
Dear Sir/Ma'am: It is significantly beneficial to your library and its patrons to have a book titled "Complete Conduct Principles for the 21st Century" by Dr. John Newton. Please suggest to your local library(ies) that the book be purchased. This is a great contribution you can make to your neighborhood! "I find it heartening that you are crusading on behalf of this
2016 Apr 01
4
RFC: std::vector and identified objects
Hi, Consider this code: std::vector v; v.resize(256); for (i = 0; i < ... ; ++i) { a += v[b[i]]; } This is a gather loop, and should be able to be vectorized. *however*... I as a programmer can see that the size of v.data() is at least 256. I know because of the contract of std::vector that v.data() is a unique heap object that doesn't alias anything. However, LLVM knows none of this.
2017 Sep 30
2
Anyone tried tinc with TCP-BBR?
I understand the concern of uncertain for TCP-over-TCP by BBR, as the BBR is natively designed to optimize TCP, instead of TCP-over-TCP, but could you articulate a bit more about the beneficial of “sending host when there is a UDP tinc tunnel” in the middle”? > On 30 Sep 2017, at 11:23 AM, Ryan Mounce <ryan at mounce.com.au> wrote: > > I'm not aware that BBR claims nor
2012 Sep 20
4
[PATCH 0/3] tsc adjust implementation for hvm
Intel recently release a new tsc adjust feature at latest SDM 17.13.3. CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. Basically it is used to simplify TSC synchronization, operation of IA32_TSC_ADJUST MSR is as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the
2009 Feb 03
6
[LLVMdev] rol/ror llvm instruction set
--- On Tue, 2/3/09, Bill Wendling <isanbard at gmail.com> wrote: > From: Bill Wendling <isanbard at gmail.com> > Subject: Re: [LLVMdev] rol/ror llvm instruction set > To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Cc: kasra_n500 at yahoo.com > Date: Tuesday, February 3, 2009, 2:52 PM > On Tue, Feb 3, 2009 at 2:45 PM, Dale Johannesen
2009 Feb 04
0
[LLVMdev] rol/ror llvm instruction set
On Feb 3, 2009, at 3:54 PM, Kasra wrote: > I guess the backends could know about the instructions. But I am not > convinced why it is beneficial not to have ROR and ROL instructions > within llvm. > How would it be beneficial to have them, if we already generate them at the target level properly? Adding instructions "just because" doesn't seem wise. -Owen
2023 Dec 28
1
User doesn't have write access to directory
On Thu, 28 Dec 2023 07:03:58 -0500 Rob Campbell via samba <samba at lists.samba.org> wrote: > I did not read that warning. It's not really an option. There are no > Windows servers and only one computer that stays on. The only other > computer that could possibly be a server is my work computer so that > can't happen. All the rest are laptops with limited space. I guess
2013 Nov 03
0
[LLVMdev] loop vectorizer issue
Hi Sarah, the loop vectorizer runs not on the C code but on LLVM IR this c code was lowered to. Before the loop vectorizer runs many other optimization change the shape of this IR. You can see in the LLVM IR you referenced below, a preceding LLVM IR transformation has change your loop from: > for(int k=20;k<50;k++) > dataY[k] = dataY[k-1]; to > int a = d[19]; >
2003 Mar 29
1
Documentation people needed. FreeBSD/Security clue beneficial.
Hi All, Ok after watching all the discussion about some security documentation and teams I have come up with a few ideas that might help out some. I'm willing to program an interface at the extremefreebsd.org site (yes I know it's still new and under some work) that will allow the following: 1. A dedicated page for security related posts (articles, docs, advisories, etc) at
2011 Oct 10
3
[LLVMdev] Disable Short-Circuit Evaluation?
Is there any way to disable short-circuit evaluation of expressions in Clang/LLVM? Let's say I have C code like the following: bool validX = get_group_id(0) > 32; int globalIndexY0 = get_group_id(1)*186 + 6*get_local_id(1) + 0 + 1; bool valid0 = validX && globalIndexY0 >= 4 && globalIndexY0 < 3910; int globalIndexY1 = get_group_id(1)*186 + 6*get_local_id(1) +
2012 Dec 30
5
[LLVMdev] [RFC] Overhauling Attributes
Hi Rafael, Sorry, I forgot to respond to this. They can be arbitrary strings that are known only to the specific back-end. It may be beneficial to define them inside of the LangRef document though. -bw On Oct 4, 2012, at 7:47 PM, Rafael Espíndola <rafael.espindola at gmail.com> wrote: >> attrgroup #1 = { "long-calls", "cpu=cortex-a8", "thumb" }
2013 Nov 03
3
[LLVMdev] loop vectorizer issue
Actually what I meant in my original loop, that there is a dependency between every two consecutive iterations. So, how the loop vectorizer says 'we can vectorize this loop'? for(int k=20;k<50;k++) dataY[k] = dataY[k-1]; From: Henrique Santos [mailto:henrique.nazare.santos at gmail.com] Sent: Sunday, November 03, 2013 4:28 PM To: Sara Elshobaky Cc: <llvmdev at
2009 Feb 04
1
[LLVMdev] rol/ror llvm instruction set
--- On Tue, 2/3/09, Owen Anderson <resistor at mac.com> wrote: > From: Owen Anderson <resistor at mac.com> > Subject: Re: [LLVMdev] rol/ror llvm instruction set > To: kasra_n500 at yahoo.com, "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Date: Tuesday, February 3, 2009, 4:20 PM > On Feb 3, 2009, at 3:54 PM, Kasra wrote: > > I guess the