search for: benefici

...third-party commercial solution, such as Crossover, Bordeaux, or whatever it is that Transgaming is offering these days, what would be the best choice in terms of contributing to Wine? I guess what I'm asking is which of the wine-based commercial solutions contributes back to Wine in the most beneficial way, whether it be through code contributed back to the Wine code base, or through other means.

Sanjoy, You have changed the subject. We still need real world examples showing how taking advantage of “undef” results in beneficial optimization. My belief is that they don’t exist, my reasoning is this: real world programmers are likely to run UBSan before compiling (or if they don’t they should), therefore it is highly unlikely that any “undef” will actually exist during compilation of their source code. Yes, “Undef” can...

All, These discussions seem to be based on the premise that there is a need for the compiler to exploit undefined behavior for performance optimization reasons. So far the only beneficial optimization I am aware of that relies on some form of “undefined” is Dan Gohman’s original project for LP64 targets of promoting i32 induction variables to i64 and hoisting sign-extension out of the loop. But “undef” / “poison” never appears in either the original or the transformed IR for thes...

We knew the TCP-BBR developed by google and try to optimize the transport efficiency of TCP, I’m wondering will this be beneficial if we put tinc in TCP mode plus the TCP-BBR?

> Sounds like threading isn't beneficial much beyond the second CPU... > Maybe blindly creating one thread per core isn't the best plan... parallel.h is pretty simplistic at the moment. Currently it creates one per SMT. One per core and being lazy about it would probably be a good thing, but threading is already beneficial and i...

...iguring-asterisk-1.6-and-postgresql-to-manage-cdr-and-realtime-config-on-debian and I noticed they suggested to recompile to 1000Hz enable kernel, I currently have a 250Hz stock standard kernel. I am running on a soekris board - amd geode cpu. Is recompiling the kernel to the 1000Hz going to be beneficial to me, the box is primarily used for firewall router / voip (Asterisk) Alex

Dear Sir/Ma'am: It is significantly beneficial to your library and its patrons to have a book titled "Complete Conduct Principles for the 21st Century" by Dr. John Newton. Please suggest to your local library(ies) that the book be purchased. This is a great contribution you can make to your neighborhood! "I find it heart...

Dear Sir/Ma'am: It is significantly beneficial to your library and its patrons to have a book titled "Complete Conduct Principles for the 21st Century" by Dr. John Newton. Please suggest to your local library(ies) that the book be purchased. This is a great contribution you can make to your neighborhood! "I find it heart...

...is about what exactly is going wrong here. I don't understand quite how we intend LLVM to gain this information - are we missing some intrinsics or abstractions? Or is the inliner just doing a poor job? I can't imagine that in the common case inlining all the way to operator new() would be beneficial - it's only beneficial in this case because the object is newly constructed so all of the branches in __append can be folded away when inlining. Any information welcome :) Cheers, James -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.or...

I understand the concern of uncertain for TCP-over-TCP by BBR, as the BBR is natively designed to optimize TCP, instead of TCP-over-TCP, but could you articulate a bit more about the beneficial of “sending host when there is a UDP tinc tunnel” in the middle”? > On 30 Sep 2017, at 11:23 AM, Ryan Mounce <ryan at mounce.com.au> wrote: > > I'm not aware that BBR claims nor attempts to resolve any of the > inherent issues with TCP-over-TCP. This should still be avoid...

Intel recently release a new tsc adjust feature at latest SDM 17.13.3. CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. Basically it is used to simplify TSC synchronization, operation of IA32_TSC_ADJUST MSR is as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the

...ways to express > rotate with shift/ > > and/or, as below. > > > Look in the DAGCombiner.cpp file to see which patterns it > translates > into ROTL and ROTR instructions. > > -bw I guess the backends could know about the instructions. But I am not convinced why it is beneficial not to have ROR and ROL instructions within llvm. > Look in the DAGCombiner.cpp file to see which patterns it > translates > into ROTL and ROTR instructions. Right, I sure will do. -- Kasra

On Feb 3, 2009, at 3:54 PM, Kasra wrote: > I guess the backends could know about the instructions. But I am not > convinced why it is beneficial not to have ROR and ROL instructions > within llvm. > How would it be beneficial to have them, if we already generate them at the target level properly? Adding instructions "just because" doesn't seem wise. -Owen

...servers and only one computer that stays on. The only other > computer that could possibly be a server is my work computer so that > can't happen. All the rest are laptops with limited space. I guess I > could spin up a vm on the DC but that doesn't seem like it would be > "beneficial". > In my opinion, it would be beneficial, because you could run a Unix domain member in that VM and use that as a fileserver and all the problems of using a DC as a fileserver go out the window. Rowland

...referenced below, a preceding LLVM IR transformation has change your loop from: > for(int k=20;k<50;k++) > dataY[k] = dataY[k-1]; to > int a = d[19]; > for(int k = 20; k < 50; k++) > dataY[k] = a; which is allowed because they are semantically equivalent and beneficial because we safe many loads. We can vectorize the latter loop. You can see in the debug output there is no load in the loop once the loop vectorizer gets to see it: > And the debug prints: > LV: Checking a loop in "main" > LV: Found a loop: for.body4 > LV: Found an inductio...

Hi All, Ok after watching all the discussion about some security documentation and teams I have come up with a few ideas that might help out some. I'm willing to program an interface at the extremefreebsd.org site (yes I know it's still new and under some work) that will allow the following: 1. A dedicated page for security related posts (articles, docs, advisories, etc) at

...*get_local_id(1) + 2 + 1; bool valid2 = validX && globalIndexY2 >= 4 && globalIndexY2 < 3910; Clang, even at -O0, is performing short-circuit evaluation of these expressions, resulting in a fair number of branch instructions being generated. For most targets, this is a beneficial optimizations. However, for my target (PTX), it would be most beneficial to actually evaluate the entire expression and remove the unneeded branches. Is this possible with current Clang/LLVM? -- Thanks, Justin Holewinski -------------- next part -------------- An HTML attachment was scrubbe...

Hi Rafael, Sorry, I forgot to respond to this. They can be arbitrary strings that are known only to the specific back-end. It may be beneficial to define them inside of the LangRef document though. -bw On Oct 4, 2012, at 7:47 PM, Rafael Espíndola <rafael.espindola at gmail.com> wrote: >> attrgroup #1 = { "long-calls", "cpu=cortex-a8", "thumb" } >> >> define void @func() noinline s...

...dency: for(int k=20;k<50;k++) dataY[k] = dataY[k-1]; And the debug prints: LV: Checking a loop in "main" LV: Found a loop: for.body4 LV: Found an induction variable. LV: Found a write-only loop! LV: We can vectorize this loop! ... LV: Vectorization is possible but not beneficial. >From the LLVM IR, it contains only one 'store' instruction with '%.pre'. Seems that no 'load' instruction prevented the Vectorizer to detect dependency. Is that a bug, or I'm missing something? Please advice for.body4:...

...t; To: kasra_n500 at yahoo.com, "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Date: Tuesday, February 3, 2009, 4:20 PM > On Feb 3, 2009, at 3:54 PM, Kasra wrote: > > I guess the backends could know about the > instructions. But I am not convinced why it is beneficial > not to have ROR and ROL instructions within llvm. > > > > How would it be beneficial to have them, if we already > generate them at the target level properly? Adding > instructions "just because" doesn't seem wise. > > -Owen If you look at it the wa...