Displaying 10 results from an estimated 10 matches for "benef".
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benet
2007 May 17
1
[PATCH] ocfs: use list_for_each_entry where benefical
Signed-off-by: Christoph Hellwig <hch@lst.de>
Index: linux-2.6/fs/ocfs2/cluster/tcp.c
===================================================================
--- linux-2.6.orig/fs/ocfs2/cluster/tcp.c 2007-05-06 13:51:17.000000000 +0200
+++ linux-2.6/fs/ocfs2/cluster/tcp.c 2007-05-17 15:00:14.000000000 +0200
@@ -261,14 +261,12 @@ out:
static void o2net_complete_nodes_nsw(struct o2net_node
2005 Dec 28
1
Ruby on rail newbie
...t have this place there.
I''m a one-year experienced php developper. I use this language for all my
web applications.
I prefer php to Java/J2ee because, of its simple features, its powerness
and the fact that it let the user
choose the way he wants to program(This is particularly benefical when i''m
prototyping)
For me the shibboleth
of j2ee is: "why make it simple when we can make it complicated".
On the other side, i find that php lacks of high level components. I mean,
you have to male your own database abstractions, and your own components to
make your...
2010 Aug 25
0
[LLVMdev] Register allocation marking spills (Re: NumLoads/NumStores for linearscan?)
...h the "local" allocator)? I still haven't grokked very well the interaction between RALinScan and Spiller... Should I add those two statistics to the spiller's class?
hmm, having information if an operation is (a, or part of a) spill generated by the register allocation would be benefical in some cases; Those memory operations cannon alias with any other memory operations in the code, so it would help Alias Analysis.
(though I'm not sure if anyone else than us at the TCE project have any use for alias analysis after regalloc)
We actually have our own hacked version of the...
2011 Jul 26
2
[LLVMdev] XOR Optimization
...hich OR is faster than ADD nor more energy-efficient. They're all done by the same ALU circuitry which delays the pipeline by its worstcase path timing. So, for modern processor hardware purposes, OR is exactly equal ADD. Transforming ADD to OR isn't strenght reduction at all. Maybe this is benefical only if you have a backend generating circuitry (programming FPGAs).
I believe that in cases where ADD and OR are equivalent, LLVM prefers the latter because it's easier to reason about the bits in the result of an OR in complex cases. The x86 backend, for instance, transforms ORs in such...
2011 Jul 26
0
[LLVMdev] XOR Optimization
...hich OR is faster than ADD nor more
energy-efficient. They're all done by the same ALU circuitry which delays
the pipeline by its worstcase path timing. So, for modern processor hardware
purposes, OR is exactly equal ADD. Transforming ADD to OR isn't strenght
reduction at all. Maybe this is benefical only if you have a backend
generating circuitry (programming FPGAs).
>
> > - Is there a straight forward way to know if an instruction belongs to
> a
> > loop? (just curiosity)
>
> I'll defer to others on this one.
>
> >
> > Thanks very much
> &g...
2010 Aug 24
2
[LLVMdev] NumLoads/NumStores for linearscan?
On Sun, Aug 15, 2010 at 10:04 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:
>
> On Aug 15, 2010, at 5:12 PM, Silvio Ricardo Cordeiro wrote:
>
> > Is there a way for me to collect statistics about the number of
> loads/stores added by the "linearscan" register allocator (just like can be
> done with the "local" allocator)? I still haven't
2011 Jul 26
2
[LLVMdev] XOR Optimization
Hi Daniel,
> Hi folks,
>
> I couldn't find a specific XOR (OR and AND) optimization on llvm, and
> therefore I am about to implement it.
> But first I would like to check with you guys that it really does not exist.
>
> For a simple loop like this:
>
> nbits = 128;
> bit_addr = 0;
> while(nbits--)
> {
> bindex=bit_addr>>5; /* Index is
2011 Jul 26
0
[LLVMdev] XOR Optimization
...an ADD nor more
> energy-efficient. They're all done by the same ALU circuitry which delays
> the pipeline by its worstcase path timing. So, for modern processor hardware
> purposes, OR is exactly equal ADD. Transforming ADD to OR isn't strenght
> reduction at all. Maybe this is benefical only if you have a backend
> generating circuitry (programming FPGAs).
>
> I believe that in cases where ADD and OR are equivalent, LLVM prefers the
> latter because it's easier to reason about the bits in the result of an OR
> in complex cases. The x86 backend, for instance,...
2015 Aug 28
2
RFC: alloca -- specify rounding factor for allocation (and more)
Hi
sorta piggybacking on the other thread. I am looking for some feedback
on how to implement the following idea in llvm.
The really short version of the idea is this:
* I want to alloca a field (record/struct), so that its size is an even
multiple of 64 bytes. [^1]
* This allocaed field will be exclusively used as an argument to functions
* llvm should be aware of the extra bytes and should
2007 Jun 05
16
CentOS Based Linux Firewall Document
I know that some of you from the list have asked me in the past for a copy of my CentOS based Linux Firewall document. There are also those that have no clue what I am talking about. This is for the former group...
There is a new version of my document out. It's changed quite a bit since the last person asked me for it. Some of the changes are:
* Updated the scripts in the Useful Shell